Home
last modified time | relevance | path

Searched refs:dpll (Results 1 – 25 of 59) sorted by relevance

123

/linux/drivers/dpll/
H A Ddpll_netlink.c34 dpll_msg_add_dev_handle(struct sk_buff *msg, struct dpll_device *dpll) in dpll_msg_add_dev_handle() argument
36 if (nla_put_u32(msg, DPLL_A_ID, dpll->id)) in dpll_msg_add_dev_handle()
63 if (xa_get_mark(&dpll_device_xa, par_ref->dpll->id, in dpll_pin_available()
110 dpll_msg_add_mode(struct sk_buff *msg, struct dpll_device *dpll, in dpll_msg_add_mode() argument
113 const struct dpll_device_ops *ops = dpll_device_ops(dpll); in dpll_msg_add_mode()
117 ret = ops->mode_get(dpll, dpll_priv(dpll), &mode, extack); in dpll_msg_add_mode()
127 dpll_msg_add_mode_supported(struct sk_buff *msg, struct dpll_device *dpll, in dpll_msg_add_mode_supported() argument
130 const struct dpll_device_ops *ops = dpll_device_ops(dpll); in dpll_msg_add_mode_supported()
138 ret = ops->mode_get(dpll, dpll_priv(dpll), &mode, extack); in dpll_msg_add_mode_supported()
148 dpll_msg_add_phase_offset_monitor(struct sk_buff *msg, struct dpll_device *dpll, in dpll_msg_add_phase_offset_monitor() argument
[all …]
H A Ddpll_core.c154 dpll_xa_ref_dpll_add(struct xarray *xa_dplls, struct dpll_device *dpll, in dpll_xa_ref_dpll_add() argument
164 if (ref->dpll != dpll) in dpll_xa_ref_dpll_add()
179 ref->dpll = dpll; in dpll_xa_ref_dpll_add()
181 ret = xa_insert(xa_dplls, dpll->id, ref, GFP_KERNEL); in dpll_xa_ref_dpll_add()
192 xa_erase(xa_dplls, dpll->id); in dpll_xa_ref_dpll_add()
208 dpll_xa_ref_dpll_del(struct xarray *xa_dplls, struct dpll_device *dpll, in dpll_xa_ref_dpll_del() argument
216 if (ref->dpll != dpll) in dpll_xa_ref_dpll_del()
245 struct dpll_device *dpll; in dpll_device_alloc() local
248 dpll = kzalloc(sizeof(*dpll), GFP_KERNEL); in dpll_device_alloc()
249 if (!dpll) in dpll_device_alloc()
[all …]
H A DMakefile6 obj-$(CONFIG_DPLL) += dpll.o
7 dpll-y += dpll_core.o
8 dpll-y += dpll_netlink.o
9 dpll-y += dpll_nl.o
H A Ddpll_core.h74 struct dpll_device *dpll; member
81 void *dpll_priv(struct dpll_device *dpll);
82 void *dpll_pin_on_dpll_priv(struct dpll_device *dpll, struct dpll_pin *pin);
85 const struct dpll_device_ops *dpll_device_ops(struct dpll_device *dpll);
H A Ddpll_netlink.h7 int dpll_device_create_ntf(struct dpll_device *dpll);
9 int dpll_device_delete_ntf(struct dpll_device *dpll);
H A DKconfig11 source "drivers/dpll/zl3073x/Kconfig"
/linux/Documentation/devicetree/bindings/clock/ti/
H A Ddpll.txt16 "ti,omap3-dpll-clock",
17 "ti,omap3-dpll-core-clock",
18 "ti,omap3-dpll-per-clock",
19 "ti,omap3-dpll-per-j-type-clock",
20 "ti,omap4-dpll-clock",
21 "ti,omap4-dpll-x2-clock",
22 "ti,omap4-dpll-core-clock",
23 "ti,omap4-dpll-m4xen-clock",
24 "ti,omap4-dpll-j-type-clock",
25 "ti,omap5-mpu-dpll-clock",
[all …]
/linux/drivers/net/ethernet/intel/ice/
H A Dice_dpll.c201 const struct dpll_device *dpll, void *dpll_priv, in ice_dpll_frequency_set() argument
239 const struct dpll_device *dpll, void *dpll_priv, in ice_dpll_input_frequency_set() argument
242 return ice_dpll_frequency_set(pin, pin_priv, dpll, dpll_priv, frequency, in ice_dpll_input_frequency_set()
264 const struct dpll_device *dpll, void *dpll_priv, in ice_dpll_output_frequency_set() argument
267 return ice_dpll_frequency_set(pin, pin_priv, dpll, dpll_priv, frequency, in ice_dpll_output_frequency_set()
290 const struct dpll_device *dpll, void *dpll_priv, in ice_dpll_frequency_get() argument
323 const struct dpll_device *dpll, void *dpll_priv, in ice_dpll_input_frequency_get() argument
326 return ice_dpll_frequency_get(pin, pin_priv, dpll, dpll_priv, frequency, in ice_dpll_input_frequency_get()
348 const struct dpll_device *dpll, void *dpll_priv, in ice_dpll_output_frequency_get() argument
351 return ice_dpll_frequency_get(pin, pin_priv, dpll, dpll_priv, frequency, in ice_dpll_output_frequency_get()
[all …]
H A Dice_dpll.h77 struct dpll_device *dpll; member
/linux/drivers/net/ethernet/mellanox/mlx5/core/
H A Ddpll.c11 struct dpll_device *dpll; member
144 mlx5_dpll_device_lock_status_get(const struct dpll_device *dpll, void *priv, in mlx5_dpll_device_lock_status_get() argument
161 static int mlx5_dpll_device_mode_get(const struct dpll_device *dpll, in mlx5_dpll_device_mode_get() argument
198 static int mlx5_dpll_clock_quality_level_get(const struct dpll_device *dpll, in mlx5_dpll_clock_quality_level_get() argument
257 const struct dpll_device *dpll, in mlx5_dpll_pin_direction_get() argument
268 const struct dpll_device *dpll, in mlx5_dpll_state_on_dpll_get() argument
286 const struct dpll_device *dpll, in mlx5_dpll_state_on_dpll_set() argument
300 const struct dpll_device *dpll, void *dpll_priv, in mlx5_dpll_ffo_get() argument
352 dpll_device_change_ntf(mdpll->dpll); in mlx5_dpll_periodic_work()
441 mdpll->dpll = dpll_device_get(clock_id, 0, THIS_MODULE); in mlx5_dpll_probe()
[all …]
/linux/drivers/dpll/zl3073x/
H A Ddpll.c45 struct zl3073x_dpll *dpll; member
92 const struct dpll_device *dpll, void *dpll_priv, in zl3073x_dpll_pin_direction_get() argument
106 const struct dpll_device *dpll, in zl3073x_dpll_input_pin_esync_get() argument
148 const struct dpll_device *dpll, in zl3073x_dpll_input_pin_esync_set() argument
181 const struct dpll_device *dpll, void *dpll_priv, in zl3073x_dpll_input_pin_ffo_get() argument
194 const struct dpll_device *dpll, in zl3073x_dpll_input_pin_frequency_get() argument
211 const struct dpll_device *dpll, in zl3073x_dpll_input_pin_frequency_set() argument
387 const struct dpll_device *dpll, in zl3073x_dpll_input_pin_phase_offset_get() argument
446 const struct dpll_device *dpll, in zl3073x_dpll_input_pin_phase_adjust_get() argument
476 const struct dpll_device *dpll, in zl3073x_dpll_input_pin_phase_adjust_set() argument
[all …]
/linux/arch/arm/mach-omap1/
H A Dsram.S36 strh r0, [r2] @ set dpll into bypass mode
41 strh r0, [r2] @ write new dpll value
49 lock: ldrh r4, [r2], #0 @ read back dpll value
52 tst r4, #1 << 0 @ dpll rate locked?
/linux/arch/arm/boot/dts/ti/omap/
H A Dam43xx-clocks.dtsi231 compatible = "ti,am3-dpll-core-clock";
237 dpll_core_x2_ck: clock-dpll-core-x2 {
239 compatible = "ti,am3-dpll-x2-clock";
244 dpll_core_m4_ck: clock-dpll-core-m4-8@2d38 {
256 dpll_core_m5_ck: clock-dpll-core-m5-8@2d3c {
268 dpll_core_m6_ck: clock-dpll-core-m6-8@2d40 {
282 compatible = "ti,am3-dpll-clock";
288 dpll_mpu_m2_ck: clock-dpll-mpu-m2-8@2d70 {
311 compatible = "ti,am3-dpll-clock";
317 dpll_ddr_m2_ck: clock-dpll-ddr-m2-8@2db0 {
[all …]
H A Dam33xx-clocks.dtsi191 compatible = "ti,am3-dpll-core-clock";
197 dpll_core_x2_ck: clock-dpll-core-x2 {
199 compatible = "ti,am3-dpll-x2-clock";
204 dpll_core_m4_ck: clock-dpll-core-m4@480 {
214 dpll_core_m5_ck: clock-dpll-core-m5@484 {
224 dpll_core_m6_ck: clock-dpll-core-m6@4d8 {
236 compatible = "ti,am3-dpll-clock";
242 dpll_mpu_m2_ck: clock-dpll-mpu-m2@4a8 {
254 compatible = "ti,am3-dpll-no-gate-clock";
260 dpll_ddr_m2_ck: clock-dpll-ddr-m2@4a0 {
[all …]
H A Domap54xx-clocks.dtsi119 compatible = "ti,omap4-dpll-m4xen-clock";
127 compatible = "ti,omap4-dpll-x2-clock";
201 compatible = "ti,omap4-dpll-core-clock";
209 compatible = "ti,omap4-dpll-x2-clock";
352 compatible = "ti,omap4-dpll-clock";
362 compatible = "ti,omap4-dpll-x2-clock";
402 compatible = "ti,omap5-mpu-dpll-clock";
586 compatible = "ti,omap4-dpll-clock";
594 compatible = "ti,omap4-dpll-x2-clock";
661 compatible = "ti,omap4-dpll-clock";
[all …]
H A Domap44xx-clocks.dtsi154 compatible = "ti,omap4-dpll-m4xen-clock";
162 compatible = "ti,omap4-dpll-x2-clock";
223 compatible = "ti,omap4-dpll-core-clock";
231 compatible = "ti,omap4-dpll-x2-clock";
390 compatible = "ti,omap4-dpll-clock";
400 compatible = "ti,omap4-dpll-x2-clock";
435 compatible = "ti,omap4-dpll-clock";
636 compatible = "ti,omap4-dpll-clock";
654 compatible = "ti,omap4-dpll-x2-clock";
748 compatible = "ti,omap4-dpll-j-type-clock";
/linux/drivers/gpu/drm/gma500/
H A Dgma_display.c223 temp = REG_READ(map->dpll); in gma_crtc_dpms()
225 REG_WRITE(map->dpll, temp); in gma_crtc_dpms()
226 REG_READ(map->dpll); in gma_crtc_dpms()
229 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
230 REG_READ(map->dpll); in gma_crtc_dpms()
233 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
234 REG_READ(map->dpll); in gma_crtc_dpms()
311 temp = REG_READ(map->dpll); in gma_crtc_dpms()
313 REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE); in gma_crtc_dpms()
314 REG_READ(map->dpll); in gma_crtc_dpms()
[all …]
H A Doaktrail_device.c144 p->dpll = PSB_RVDC32(MRST_DPLL_A); in oaktrail_save_display_registers()
261 PSB_WVDC32(p->dpll, MRST_DPLL_A); in oaktrail_restore_display_registers()
402 .dpll = MRST_DPLL_A,
426 .dpll = DPLL_B,
H A Dpsb_device.c204 .dpll = DPLL_A,
228 .dpll = DPLL_B,
/linux/drivers/ata/
H A Dpata_hpt3x2n.c312 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_defer() local
319 if ((flags & USE_DPLL) != dpll && alt->qc_active) in hpt3x2n_qc_defer()
328 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_issue() local
330 if ((flags & USE_DPLL) != dpll) { in hpt3x2n_qc_issue()
332 flags |= dpll; in hpt3x2n_qc_issue()
335 hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23); in hpt3x2n_qc_issue()
H A Dpata_hpt37x.c948 int dpll, adjust; in hpt37x_init_one() local
951 dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2; in hpt37x_init_one()
953 f_low = (MHz[clock_slot] * 48) / MHz[dpll]; in hpt37x_init_one()
981 if (dpll == 3) in hpt37x_init_one()
987 MHz[clock_slot], MHz[dpll]); in hpt37x_init_one()
/linux/arch/arm64/boot/dts/sprd/
H A Dsharkl3.dtsi123 dpll: dpll@0 { label
124 compatible = "sprd,sc9863a-dpll";
/linux/Documentation/devicetree/bindings/phy/
H A Dti-phy.txt46 * "dpll_ref" - external dpll ref clk
47 * "dpll_ref_m2" - external dpll ref clk
/linux/drivers/clk/ti/
H A DMakefile5 clk-common = dpll.o composite.o divider.o gate.o \
/linux/arch/arm/mach-omap2/
H A Dsram242x.S254 str r0, [r4] @ set dpll ctrl val
267 beq pend @ jump over dpll relock
272 orr r8, r7, #0x3 @ val for lock dpll

123