/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/ |
H A D | dml2_pmo_dcn4_fams2.c | 295 if (in_out->display_config != in_out->optimized_display_cfg) { in pmo_dcn4_fams2_optimize_dcc_mcache() 296 memcpy(in_out->optimized_display_cfg, in_out->display_config, sizeof(struct dml2_display_cfg)); in pmo_dcn4_fams2_optimize_dcc_mcache() 714 const struct dml2_display_cfg *display_config = in pmo_dcn4_fams2_init_for_vmin() local 715 &in_out->base_display_config->display_config; in pmo_dcn4_fams2_init_for_vmin() 722 (in_out->instance->options->disable_dyn_odm_for_multi_stream && display_config->num_streams > 1)) in pmo_dcn4_fams2_init_for_vmin() 725 for (i = 0; i < display_config->num_planes; i++) in pmo_dcn4_fams2_init_for_vmin() 739 …mode_support_result->cfg_support_info.stream_support_info[display_config->plane_descriptors[i].str… in pmo_dcn4_fams2_init_for_vmin() 740 state->unoptimizable_streams[display_config->plane_descriptors[i].stream_index] = true; in pmo_dcn4_fams2_init_for_vmin() 742 for (i = 0; i < display_config->num_streams; i++) { in pmo_dcn4_fams2_init_for_vmin() 743 if (display_config->stream_descriptors[i].overrides.disable_dynamic_odm) in pmo_dcn4_fams2_init_for_vmin() [all …]
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H A D | dml2_pmo_dcn3.c | 25 for (unsigned int i = 0; i < config->display_config.num_planes; i++) { in get_max_reserved_time_on_all_planes_with_stream_index() 26 plane_descriptor = &config->display_config.plane_descriptors[i]; in get_max_reserved_time_on_all_planes_with_stream_index() 41 for (unsigned int i = 0; i < config->display_config.num_planes; i++) { in set_reserved_time_on_all_planes_with_stream_index() 42 plane_descriptor = &config->display_config.plane_descriptors[i]; in set_reserved_time_on_all_planes_with_stream_index() 196 …e_timings_trivially_synchronizable(struct display_configuation_with_meta *display_config, int mask) in are_timings_trivially_synchronizable() argument 205 for (i = 0; i < display_config->display_config.num_streams; i++) { in are_timings_trivially_synchronizable() 216 if (memcmp(&display_config->display_config.stream_descriptors[remap_array[i - 1]].timing, in are_timings_trivially_synchronizable() 217 &display_config->display_config.stream_descriptors[remap_array[i]].timing, in are_timings_trivially_synchronizable() 225 if (display_config->display_config.stream_descriptors[remap_array[i]].timing.drr_config.enabled) { in are_timings_trivially_synchronizable() 282 const struct dml2_display_cfg *display_config = in pmo_dcn3_init_for_vmin() local [all …]
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/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/ |
H A D | dml2_top_optimization.c | 16 struct dml2_optimization_stage1_state *state = ¶ms->display_config->stage1; in dml2_top_optimization_init_function_min_clk_for_latency() 25 struct dml2_optimization_stage1_state *state = ¶ms->display_config->stage1; in dml2_top_optimization_test_function_min_clk_for_latency() 34 if (params->display_config->stage1.min_clk_index_for_latency > 0) { in dml2_top_optimization_optimize_function_min_clk_for_latency() 35 copy_display_configuration_with_meta(params->optimized_display_config, params->display_config); in dml2_top_optimization_optimize_function_min_clk_for_latency() 52 l->test_mcache.calc_mcache_count_params.display_config = ¶ms->display_config->display_config; in dml2_top_optimization_test_function_mcache() 53 …l->test_mcache.calc_mcache_count_params.mcache_allocations = params->display_config->stage2.mcache… in dml2_top_optimization_test_function_mcache() 58 …l->test_mcache.assign_global_mcache_ids_params.allocations = params->display_config->stage2.mcache… in dml2_top_optimization_test_function_mcache() 59 …he.assign_global_mcache_ids_params.num_allocations = params->display_config->display_config.num_pl… in dml2_top_optimization_test_function_mcache() 64 …l->test_mcache.validate_admissibility_params.display_cfg = ¶ms->display_config->display_config; in dml2_top_optimization_test_function_mcache() 65 …l->test_mcache.validate_admissibility_params.mcache_allocations = params->display_config->stage2.m… in dml2_top_optimization_test_function_mcache() [all …]
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H A D | dml_top.c | 83 …ce *dml, struct display_configuation_with_meta *out, const struct dml2_display_cfg *display_config) in setup_unoptimized_display_config_with_meta() argument 85 memcpy(&out->display_config, display_config, sizeof(struct dml2_display_cfg)); in setup_unoptimized_display_config_with_meta() 89 …ce *dml, struct display_configuation_with_meta *out, const struct dml2_display_cfg *display_config) in setup_speculative_display_config_with_meta() argument 91 memcpy(&out->display_config, display_config, sizeof(struct dml2_display_cfg)); in setup_speculative_display_config_with_meta() 106 …optimized_display_config_with_meta(dml, &l->base_display_config_with_meta, in_out->display_config); in dml2_check_mode_supported() 119 .display_config = &l->base_display_config_with_meta, in dml2_check_mode_supported() 161 …memcpy(&in_out->programming->display_config, in_out->display_config, sizeof(struct dml2_display_cf… in dml2_build_mode_programming() 163 …eculative_display_config_with_meta(dml, &l->base_display_config_with_meta, in_out->display_config); in dml2_build_mode_programming() 174 …optimized_display_config_with_meta(dml, &l->base_display_config_with_meta, in_out->display_config); in dml2_build_mode_programming() 198 l->min_clock_for_latency_phase.display_config = &l->base_display_config_with_meta; in dml2_build_mode_programming() [all …]
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H A D | dml_top_mcache.c | 519 for (i = 0; i < params->display_config->num_planes; i++) { in dml2_top_mcache_calc_mcache_count_and_offsets() 520 if (!params->display_config->plane_descriptors[i].surface.dcc.enable) { in dml2_top_mcache_calc_mcache_count_and_offsets() 525 l->calc_mcache_params.plane_descriptor = ¶ms->display_config->plane_descriptors[i]; in dml2_top_mcache_calc_mcache_count_and_offsets()
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/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/ |
H A D | dml2_core_dcn4.c | 196 memcpy(svp_expanded_display_cfg, &display_cfg->display_config, sizeof(struct dml2_display_cfg)); in expand_implict_subvp() 201 if (!display_cfg->display_config.overrides.enable_subvp_implicit_pmo) in expand_implict_subvp() 210 for (stream_index = 0; stream_index < display_cfg->display_config.num_streams; stream_index++) { in expand_implict_subvp() 211 main_stream = &display_cfg->display_config.stream_descriptors[stream_index]; in expand_implict_subvp() 230 for (plane_index = 0; plane_index < display_cfg->display_config.num_planes; plane_index++) { in expand_implict_subvp() 231 main_plane = &display_cfg->display_config.plane_descriptors[plane_index]; in expand_implict_subvp() 234 main_stream = &display_cfg->display_config.stream_descriptors[main_plane->stream_index]; in expand_implict_subvp() 264 …memcpy(&programming->display_config, &display_cfg->display_config, sizeof(struct dml2_display_cfg)… in pack_mode_programming_params_with_implicit_subvp() 267 …dml2_core_calcs_get_arb_params(&display_cfg->display_config, &core->clean_me_up.mode_lib, &program… in pack_mode_programming_params_with_implicit_subvp() 270 …dml2_core_calcs_get_watermarks(&display_cfg->display_config, &core->clean_me_up.mode_lib, &program… in pack_mode_programming_params_with_implicit_subvp() [all …]
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H A D | dml2_core_utils.c | 462 memcpy(svp_expanded_display_cfg, &display_cfg->display_config, sizeof(struct dml2_display_cfg)); in dml2_core_utils_expand_implict_subvp() 467 if (!display_cfg->display_config.overrides.enable_subvp_implicit_pmo) in dml2_core_utils_expand_implict_subvp() 476 for (stream_index = 0; stream_index < display_cfg->display_config.num_streams; stream_index++) { in dml2_core_utils_expand_implict_subvp() 477 main_stream = &display_cfg->display_config.stream_descriptors[stream_index]; in dml2_core_utils_expand_implict_subvp() 496 for (plane_index = 0; plane_index < display_cfg->display_config.num_planes; plane_index++) { in dml2_core_utils_expand_implict_subvp() 497 main_plane = &display_cfg->display_config.plane_descriptors[plane_index]; in dml2_core_utils_expand_implict_subvp() 500 main_stream = &display_cfg->display_config.stream_descriptors[main_plane->stream_index]; in dml2_core_utils_expand_implict_subvp()
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/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/ |
H A D | dml21_wrapper.c | 27 (*dml_ctx)->v21.mode_support.display_config = &(*dml_ctx)->v21.display_config; in dml21_allocate_memory() 28 (*dml_ctx)->v21.mode_programming.display_config = (*dml_ctx)->v21.mode_support.display_config; in dml21_allocate_memory() 198 memset(&dml_ctx->v21.display_config, 0, sizeof(struct dml2_display_cfg)); in dml21_mode_check_and_programming() 255 memset(&dml_ctx->v21.display_config, 0, sizeof(struct dml2_display_cfg)); in dml21_check_mode_support() 307 dml_phantom_prog_idx = dml_ctx->v21.mode_programming.programming->display_config.num_planes; in dml21_prepare_mcache_programming() 310 …for (dml_prog_idx = 0; dml_prog_idx < dml_ctx->v21.mode_programming.programming->display_config.nu… in dml21_prepare_mcache_programming() 361 …for (dml_prog_idx = 0; dml_prog_idx < dml_ctx->v21.mode_programming.programming->display_config.nu… in dml21_prepare_mcache_programming() 418 dst_dml_ctx->v21.mode_support.display_config = &dst_dml_ctx->v21.display_config; in dml21_copy() 419 dst_dml_ctx->v21.mode_programming.display_config = dst_dml_ctx->v21.mode_support.display_config; in dml21_copy()
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H A D | dml21_utils.c | 430 …x = 0; dml_stream_index < dml_ctx->v21.mode_programming.programming->display_config.num_streams; d… in dml21_handle_phantom_streams_planes() 453 …ex = 0; dml_plane_index < dml_ctx->v21.mode_programming.programming->display_config.num_planes; dm… in dml21_handle_phantom_streams_planes()
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/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
H A D | hardwaremanager.c | 305 const struct amd_pp_display_configuration *display_config) in phm_store_dal_configuration_data() argument 312 if (display_config == NULL) in phm_store_dal_configuration_data() 316 hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk(hwmgr, display_config->min_dcef_deep_sleep_set_clk); in phm_store_dal_configuration_data() 318 for (index = 0; index < display_config->num_path_including_non_display; index++) { in phm_store_dal_configuration_data() 319 if (display_config->displays[index].controller_id != 0) in phm_store_dal_configuration_data() 333 display_config->cpu_pstate_separation_time, in phm_store_dal_configuration_data() 334 display_config->cpu_cc6_disable, in phm_store_dal_configuration_data() 335 display_config->cpu_pstate_disable, in phm_store_dal_configuration_data() 336 display_config->nb_pstate_switch_disable); in phm_store_dal_configuration_data()
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H A D | vega12_hwmgr.c | 1623 if ((hwmgr->display_config->num_display > 1) && in vega12_notify_smc_display_config_after_ps_adjustment() 1624 !hwmgr->display_config->multi_monitor_in_sync && in vega12_notify_smc_display_config_after_ps_adjustment() 1625 !hwmgr->display_config->nb_pstate_switch_disable) in vega12_notify_smc_display_config_after_ps_adjustment() 1630 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; in vega12_notify_smc_display_config_after_ps_adjustment() 1631 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk; in vega12_notify_smc_display_config_after_ps_adjustment() 1632 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega12_notify_smc_display_config_after_ps_adjustment() 2366 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && in vega12_apply_clocks_adjust_rules() 2367 !hwmgr->display_config->multi_monitor_in_sync) || in vega12_apply_clocks_adjust_rules() 2369 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; in vega12_apply_clocks_adjust_rules() 2420 if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100)) in vega12_apply_clocks_adjust_rules() [all …]
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H A D | vega20_hwmgr.c | 2358 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; in vega20_notify_smc_display_config_after_ps_adjustment() 2359 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk; in vega20_notify_smc_display_config_after_ps_adjustment() 2360 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega20_notify_smc_display_config_after_ps_adjustment() 3673 hwmgr->display_config->num_display, in vega20_display_configuration_changed_task() 3748 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && in vega20_apply_clocks_adjust_rules() 3749 !hwmgr->display_config->multi_monitor_in_sync) || in vega20_apply_clocks_adjust_rules() 3751 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; in vega20_apply_clocks_adjust_rules() 3802 if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100)) in vega20_apply_clocks_adjust_rules() 3803 dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100; in vega20_apply_clocks_adjust_rules() 3810 if (dpm_table->dpm_levels[i].value >= (hwmgr->display_config->min_mem_set_clock / 100)) { in vega20_apply_clocks_adjust_rules() [all …]
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H A D | smu10_hwmgr.c | 194 clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; in smu10_set_clock_limit() 628 uint32_t min_sclk = hwmgr->display_config->min_core_set_clock; in smu10_dpm_force_dpm_level() 629 uint32_t min_mclk = hwmgr->display_config->min_mem_set_clock/100; in smu10_dpm_force_dpm_level() 785 hwmgr->display_config->num_display > 3 ? in smu10_dpm_force_dpm_level()
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H A D | smu7_hwmgr.c | 3356 minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock; in smu7_apply_state_adjust_rules() 3357 minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in smu7_apply_state_adjust_rules() 3387 disable_mclk_switching_for_display = ((1 < hwmgr->display_config->num_display) && in smu7_apply_state_adjust_rules() 3388 !hwmgr->display_config->multi_monitor_in_sync) || in smu7_apply_state_adjust_rules() 3389 (hwmgr->display_config->num_display && in smu7_apply_state_adjust_rules() 3390 smu7_vblank_too_short(hwmgr, hwmgr->display_config->min_vblank_time)); in smu7_apply_state_adjust_rules() 3395 if (hwmgr->display_config->num_display == 0) { in smu7_apply_state_adjust_rules() 3437 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; in smu7_apply_state_adjust_rules() 4131 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) in smu7_find_dpm_states_clocks_in_dpm_table() 4588 …display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (hwmgr->display_config->nu… in smu7_program_display_gap() [all …]
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H A D | vega10_hwmgr.c | 3328 minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock; in vega10_apply_state_adjust_rules() 3329 minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega10_apply_state_adjust_rules() 3369 if (hwmgr->display_config->num_display == 0) in vega10_apply_state_adjust_rules() 3372 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && in vega10_apply_state_adjust_rules() 3373 !hwmgr->display_config->multi_monitor_in_sync) || in vega10_apply_state_adjust_rules() 3405 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; in vega10_apply_state_adjust_rules() 3475 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) in vega10_find_dpm_states_clocks_in_dpm_table() 4110 if ((hwmgr->display_config->num_display > 1) && in vega10_notify_smc_display_config_after_ps_adjustment() 4111 !hwmgr->display_config->multi_monitor_in_sync && in vega10_notify_smc_display_config_after_ps_adjustment() 4112 !hwmgr->display_config->nb_pstate_switch_disable) in vega10_notify_smc_display_config_after_ps_adjustment() [all …]
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H A D | smu8_hwmgr.c | 711 clock = hwmgr->display_config->min_core_set_clock; in smu8_update_sclk_limit() 769 uint32_t clks = hwmgr->display_config->min_core_set_clock_in_sr; in smu8_set_deep_sleep_sclk_threshold() 1093 clocks.memoryClock = hwmgr->display_config->min_mem_set_clock != 0 ? in smu8_apply_state_adjust_rules() 1094 hwmgr->display_config->min_mem_set_clock : in smu8_apply_state_adjust_rules() 1102 || (hwmgr->display_config->num_display >= 3); in smu8_apply_state_adjust_rules()
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/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/inc/ |
H A D | dml2_internal_shared_types.h | 339 struct dml2_display_cfg display_config; member 503 const struct dml2_display_cfg *display_config; member 526 const struct display_configuation_with_meta *display_config; member 795 const struct dml2_display_cfg *display_config; member 890 struct display_configuation_with_meta *display_config; member 896 struct display_configuation_with_meta *display_config; member 903 struct display_configuation_with_meta *display_config; member 909 const struct display_configuation_with_meta *display_config; // Initial Display Configuration member 964 const struct dml2_display_cfg *display_config; member
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/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/ |
H A D | dml2_dpmm_dcn4.c | 60 if (in_out->display_cfg->display_config.hostvm_enable) in calculate_system_active_minimums() 357 for (i = 0; i < display_cfg->display_config.num_streams; i++) { in map_min_clocks_to_dpm() 375 static bool are_timings_trivially_synchronizable(struct dml2_display_cfg *display_config, int mask) in are_timings_trivially_synchronizable() argument 384 for (i = 0; i < display_config->num_streams; i++) { in are_timings_trivially_synchronizable() 396 …if (memcmp(&display_config->stream_descriptors[remap_array[i - 1]].timing, &display_config->stream… in are_timings_trivially_synchronizable() 404 if (display_config->stream_descriptors[remap_array[i]].timing.drr_config.enabled) { in are_timings_trivially_synchronizable() 423 for (i = 0; i < in_out->programming->display_config.num_streams; i++) { in find_smallest_idle_time_in_vblank_us() 446 if (are_timings_trivially_synchronizable(&in_out->programming->display_config, 0xF)) { in determine_power_management_features_with_vblank_only() 465 for (i = 0; i < in_out->programming->display_config.num_planes; i++) { in get_displays_without_vactive_margin_mask() 479 for (i = 0; i < in_out->programming->display_config.num_planes; i++) { in get_displays_with_fams_mask() [all …]
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/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/ |
H A D | dml_top_types.h | 110 const struct dml2_display_cfg *display_config; member 367 struct dml2_display_cfg display_config; member 686 const struct dml2_display_cfg *display_config; member
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/linux/arch/arm/mach-davinci/ |
H A D | da8xx.h | 76 (struct vpif_display_config *display_config);
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H A D | da850.c | 333 *display_config) in da850_register_vpif_display() 335 da850_vpif_display_dev.dev.platform_data = display_config; in da850_register_vpif_display()
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/linux/drivers/gpu/drm/amd/display/dc/dml2/ |
H A D | dml2_internal_types.h | 149 struct dml2_display_cfg display_config; member
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/linux/drivers/gpu/drm/amd/pm/powerplay/inc/ |
H A D | hardwaremanager.h | 428 const struct amd_pp_display_configuration *display_config);
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/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
H A D | vegam_smumgr.c | 839 data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr; in vegam_populate_single_graphic_level() 843 hwmgr->display_config->min_core_set_clock_in_sr); in vegam_populate_single_graphic_level() 1013 data->display_timing.num_existing_displays = hwmgr->display_config->num_display; in vegam_populate_single_memory_level() 1014 data->display_timing.vrefresh = hwmgr->display_config->vrefresh; in vegam_populate_single_memory_level()
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H A D | fiji_smumgr.c | 974 data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr; in fiji_populate_single_graphic_level() 978 hwmgr->display_config->min_core_set_clock_in_sr); in fiji_populate_single_graphic_level() 1199 data->display_timing.num_existing_displays = hwmgr->display_config->num_display; in fiji_populate_single_memory_level() 1200 data->display_timing.vrefresh = hwmgr->display_config->vrefresh; in fiji_populate_single_memory_level()
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