| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/ |
| H A D | dml21_wrapper.c | 37 (*dml_ctx)->v21.mode_support.display_config = &(*dml_ctx)->v21.display_config; in dml21_allocate_memory()
38 (*dml_ctx)->v21.mode_programming.display_config = (*dml_ctx)->v21.mode_support.display_config; in dml21_allocate_memory()
85 dst_dml_ctx->v21.mode_support.display_config = &dst_dml_ctx->v21.display_config; in dml21_copy()
86 dst_dml_ctx->v21.mode_programming.display_config = dst_dml_ctx->v21.mode_support.display_config; in dml21_copy()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/ |
| H A D | dml2_pmo_dcn6_stage_optimizers.c | 423 const struct dml2_display_cfg *display_config = worksheet->orig_dispcfg; in dcn6_update_worksheet_for_pstate_admissibility() local
432 if (display_config->num_streams > 1) { in dcn6_update_worksheet_for_pstate_admissibility()
437 ideal_relative_disallow = (double)math_pow(0.5, (float)(display_config->num_streams - 1)) * 0.95; in dcn6_update_worksheet_for_pstate_admissibility()
440 for (stream_index = 0; stream_index < display_config->num_streams; stream_index++) { in dcn6_update_worksheet_for_pstate_admissibility()
449 vblank_time_us = display_config->stream_descriptors[stream_index].timing.vblank_nom * in dcn6_update_worksheet_for_pstate_admissibility()
483 for (plane_index = 0; plane_index < display_config->num_planes; plane_index++) { in dcn6_update_worksheet_for_pstate_admissibility()
484 if (display_config->plane_descriptors[plane_index].stream_index != stream_index) { in dcn6_update_worksheet_for_pstate_admissibility()
584 const struct dml2_display_cfg *display_config, in dcn6_all_timings_support_vactive() argument
592 for (i = 0; i < display_config->num_streams; i++) { in dcn6_all_timings_support_vactive()
596 display_config->num_streams == 1; in dcn6_all_timings_support_vactive()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/ |
| H A D | dml2_core_utils.c | 618 memcpy(svp_expanded_display_cfg, &display_cfg->display_config, sizeof(struct dml2_display_cfg)); in dml2_core_utils_expand_implict_subvp()
623 if (!display_cfg->display_config.overrides.enable_subvp_implicit_pmo) in dml2_core_utils_expand_implict_subvp()
632 for (stream_index = 0; stream_index < display_cfg->display_config.num_streams; stream_index++) { in dml2_core_utils_expand_implict_subvp()
633 main_stream = &display_cfg->display_config.stream_descriptors[stream_index]; in dml2_core_utils_expand_implict_subvp()
652 for (plane_index = 0; plane_index < display_cfg->display_config.num_planes; plane_index++) { in dml2_core_utils_expand_implict_subvp()
653 main_plane = &display_cfg->display_config.plane_descriptors[plane_index]; in dml2_core_utils_expand_implict_subvp()
656 main_stream = &display_cfg->display_config.stream_descriptors[main_plane->stream_index]; in dml2_core_utils_expand_implict_subvp()
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| H A D | dml2_core_dcn5_funcs_mode_programming.c | 1611 memcpy(&programming->display_config, mode_prog->in_display_cfg, sizeof(struct dml2_display_cfg)); in dcn5_pack_mode_programming_params()
1613 …dcn5_get_arb_params(&programming->display_config, mode_lib, utm_soc_bb, &programming->global_regs.… in dcn5_pack_mode_programming_params()
1615 …dcn5_get_watermarks(&programming->display_config, mode_lib, utm_soc_bb, &programming->global_regs.… in dcn5_pack_mode_programming_params()
1630 DML_LOG_VERBOSE("DML::%s: num_planes=%d\n", __func__, programming->display_config.num_planes); in dcn5_pack_mode_programming_params()
1632 for (plane_index = 0; plane_index < programming->display_config.num_planes; plane_index++) { in dcn5_pack_mode_programming_params()
1651 …programming->plane_programming[plane_index].plane_descriptor = &programming->display_config.plane_… in dcn5_pack_mode_programming_params()
1659 …dcn5_get_pipe_regs(&programming->display_config, mode_lib, programming->plane_programming[plane_in… in dcn5_pack_mode_programming_params()
1661 main_stream_index = programming->display_config.plane_descriptors[plane_index].stream_index; in dcn5_pack_mode_programming_params()
1666 …eam_programming[main_stream_index].stream_descriptor = &programming->display_config.stream_descrip… in dcn5_pack_mode_programming_params()
1680 …for (dwb_index = 0; dwb_index < programming->display_config.stream_descriptors[main_stream_index].… in dcn5_pack_mode_programming_params()
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| /linux/arch/arm/mach-davinci/ |
| H A D | da8xx.h | 74 (struct vpif_display_config *display_config);
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| /linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| H A D | vega12_hwmgr.c | 1623 if ((hwmgr->display_config->num_display > 1) && in vega12_notify_smc_display_config_after_ps_adjustment()
1624 !hwmgr->display_config->multi_monitor_in_sync && in vega12_notify_smc_display_config_after_ps_adjustment()
1625 !hwmgr->display_config->nb_pstate_switch_disable) in vega12_notify_smc_display_config_after_ps_adjustment()
1630 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; in vega12_notify_smc_display_config_after_ps_adjustment()
1631 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk; in vega12_notify_smc_display_config_after_ps_adjustment()
1632 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega12_notify_smc_display_config_after_ps_adjustment()
2369 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && in vega12_apply_clocks_adjust_rules()
2370 !hwmgr->display_config->multi_monitor_in_sync) || in vega12_apply_clocks_adjust_rules()
2372 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; in vega12_apply_clocks_adjust_rules()
2423 if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100)) in vega12_apply_clocks_adjust_rules()
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| H A D | vega20_hwmgr.c | 2359 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; in vega20_notify_smc_display_config_after_ps_adjustment()
2360 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk; in vega20_notify_smc_display_config_after_ps_adjustment()
2361 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega20_notify_smc_display_config_after_ps_adjustment()
3711 hwmgr->display_config->num_display, in vega20_display_configuration_changed_task()
3786 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && in vega20_apply_clocks_adjust_rules()
3787 !hwmgr->display_config->multi_monitor_in_sync) || in vega20_apply_clocks_adjust_rules()
3789 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; in vega20_apply_clocks_adjust_rules()
3840 if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100)) in vega20_apply_clocks_adjust_rules()
3841 dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100; in vega20_apply_clocks_adjust_rules()
3848 if (dpm_table->dpm_levels[i].value >= (hwmgr->display_config->min_mem_set_clock / 100)) { in vega20_apply_clocks_adjust_rules()
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| H A D | smu7_hwmgr.c | 3173 const struct amd_pp_display_configuration *cfg = hwmgr->display_config; in smu7_lookup_vddc_from_dispclk()
3472 minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock; in smu7_apply_state_adjust_rules()
3473 minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in smu7_apply_state_adjust_rules()
3503 disable_mclk_switching_for_display = ((1 < hwmgr->display_config->num_display) && in smu7_apply_state_adjust_rules()
3504 !hwmgr->display_config->multi_monitor_in_sync) || in smu7_apply_state_adjust_rules()
3505 (hwmgr->display_config->num_display && in smu7_apply_state_adjust_rules()
3506 smu7_vblank_too_short(hwmgr, hwmgr->display_config->min_vblank_time)); in smu7_apply_state_adjust_rules()
3511 if (hwmgr->display_config->num_display == 0) { in smu7_apply_state_adjust_rules()
3553 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; in smu7_apply_state_adjust_rules()
4247 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) in smu7_find_dpm_states_clocks_in_dpm_table()
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| /linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| H A D | vegam_smumgr.c | 839 data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr; in vegam_populate_single_graphic_level()
843 hwmgr->display_config->min_core_set_clock_in_sr); in vegam_populate_single_graphic_level()
1013 data->display_timing.num_existing_displays = hwmgr->display_config->num_display; in vegam_populate_single_memory_level()
1014 data->display_timing.vrefresh = hwmgr->display_config->vrefresh; in vegam_populate_single_memory_level()
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| H A D | fiji_smumgr.c | 974 data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr; in fiji_populate_single_graphic_level()
978 hwmgr->display_config->min_core_set_clock_in_sr); in fiji_populate_single_graphic_level()
1199 data->display_timing.num_existing_displays = hwmgr->display_config->num_display; in fiji_populate_single_memory_level()
1200 data->display_timing.vrefresh = hwmgr->display_config->vrefresh; in fiji_populate_single_memory_level()
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| H A D | polaris10_smumgr.c | 993 data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr; in polaris10_populate_single_graphic_level()
997 hwmgr->display_config->min_core_set_clock_in_sr); in polaris10_populate_single_graphic_level()
1188 data->display_timing.num_existing_displays = hwmgr->display_config->num_display; in polaris10_populate_single_memory_level()
1189 data->display_timing.vrefresh = hwmgr->display_config->vrefresh; in polaris10_populate_single_memory_level()
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| H A D | iceland_smumgr.c | 932 hwmgr->display_config->min_core_set_clock_in_sr; in iceland_populate_single_graphic_level()
1282 data->display_timing.num_existing_displays = hwmgr->display_config->num_display; in iceland_populate_single_memory_level()
1283 data->display_timing.vrefresh = hwmgr->display_config->vrefresh; in iceland_populate_single_memory_level()
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| H A D | tonga_smumgr.c | 659 hwmgr->display_config->min_core_set_clock_in_sr; in tonga_populate_single_graphic_level()
1016 data->display_timing.num_existing_displays = hwmgr->display_config->num_display; in tonga_populate_single_memory_level()
1017 data->display_timing.vrefresh = hwmgr->display_config->vrefresh; in tonga_populate_single_memory_level()
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| H A D | ci_smumgr.c | 1235 data->display_timing.num_existing_displays = hwmgr->display_config->num_display; in ci_populate_single_memory_level()
1236 data->display_timing.vrefresh = hwmgr->display_config->vrefresh; in ci_populate_single_memory_level()
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