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Searched refs:display_config (Results 1 – 25 of 28) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/
H A Ddml2_pmo_dcn4_fams2.c299 if (in_out->display_config != in_out->optimized_display_cfg) { in pmo_dcn4_fams2_optimize_dcc_mcache()
300 memcpy(in_out->optimized_display_cfg, in_out->display_config, sizeof(struct dml2_display_cfg)); in pmo_dcn4_fams2_optimize_dcc_mcache()
773 const struct dml2_display_cfg *display_config = in pmo_dcn4_fams2_init_for_vmin() local
774 &in_out->base_display_config->display_config; in pmo_dcn4_fams2_init_for_vmin()
781 (in_out->instance->options->disable_dyn_odm_for_multi_stream && display_config->num_streams > 1)) in pmo_dcn4_fams2_init_for_vmin()
784 for (i = 0; i < display_config->num_planes; i++) in pmo_dcn4_fams2_init_for_vmin()
798 mode_support_result->cfg_support_info.stream_support_info[display_config->plane_descriptors[i].stream_index].odms_used == 1) in pmo_dcn4_fams2_init_for_vmin()
799 state->unoptimizable_streams[display_config->plane_descriptors[i].stream_index] = true; in pmo_dcn4_fams2_init_for_vmin()
801 for (i = 0; i < display_config->num_streams; i++) { in pmo_dcn4_fams2_init_for_vmin()
802 if (display_config in pmo_dcn4_fams2_init_for_vmin()
838 find_highest_odm_load_stream_index(const struct dml2_display_cfg * display_config,const struct dml2_core_mode_support_result * mode_support_result) find_highest_odm_load_stream_index() argument
863 const struct dml2_display_cfg *display_config = pmo_dcn4_fams2_optimize_for_vmin() local
964 build_synchronized_timing_groups(struct dml2_pmo_instance * pmo,struct display_configuation_with_meta * display_config) build_synchronized_timing_groups() argument
1019 all_timings_support_vactive(const struct dml2_pmo_instance * pmo,const struct display_configuation_with_meta * display_config,unsigned int mask) all_timings_support_vactive() argument
1037 all_timings_support_vblank(const struct dml2_pmo_instance * pmo,const struct display_configuation_with_meta * display_config,unsigned int mask) all_timings_support_vblank() argument
1068 all_timings_support_drr(const struct dml2_pmo_instance * pmo,const struct display_configuation_with_meta * display_config,unsigned int mask) all_timings_support_drr() argument
1106 all_timings_support_svp(const struct dml2_pmo_instance * pmo,const struct display_configuation_with_meta * display_config,unsigned int mask) all_timings_support_svp() argument
1696 build_pstate_meta_per_stream(struct dml2_pmo_instance * pmo,struct display_configuation_with_meta * display_config,int stream_index) build_pstate_meta_per_stream() argument
1850 build_subvp_meta_per_stream(struct dml2_pmo_instance * pmo,struct display_configuation_with_meta * display_config,int stream_index) build_subvp_meta_per_stream() argument
1871 struct display_configuation_with_meta *display_config; pmo_dcn4_fams2_init_for_pstate_support() local
1966 reset_display_configuration(struct display_configuation_with_meta * display_config) reset_display_configuration() argument
1993 setup_planes_for_drr_by_mask(struct display_configuation_with_meta * display_config,struct dml2_pmo_instance * pmo,int plane_mask) setup_planes_for_drr_by_mask() argument
2012 setup_planes_for_svp_by_mask(struct display_configuation_with_meta * display_config,struct dml2_pmo_instance * pmo,int plane_mask) setup_planes_for_svp_by_mask() argument
2035 setup_planes_for_svp_drr_by_mask(struct display_configuation_with_meta * display_config,struct dml2_pmo_instance * pmo,int plane_mask) setup_planes_for_svp_drr_by_mask() argument
2058 setup_planes_for_vblank_by_mask(struct display_configuation_with_meta * display_config,struct dml2_pmo_instance * pmo,int plane_mask) setup_planes_for_vblank_by_mask() argument
2077 setup_planes_for_vblank_drr_by_mask(struct display_configuation_with_meta * display_config,struct dml2_pmo_instance * pmo,int plane_mask) setup_planes_for_vblank_drr_by_mask() argument
2095 setup_planes_for_vactive_by_mask(struct display_configuation_with_meta * display_config,struct dml2_pmo_instance * pmo,int plane_mask) setup_planes_for_vactive_by_mask() argument
2116 setup_planes_for_vactive_drr_by_mask(struct display_configuation_with_meta * display_config,struct dml2_pmo_instance * pmo,int plane_mask) setup_planes_for_vactive_drr_by_mask() argument
2137 setup_display_config(struct display_configuation_with_meta * display_config,struct dml2_pmo_instance * pmo,int strategy_index) setup_display_config() argument
2186 dcn4_get_minimum_reserved_time_us_for_planes(const struct display_configuation_with_meta * display_config,int plane_mask) dcn4_get_minimum_reserved_time_us_for_planes() argument
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H A Ddml2_pmo_dcn42.c71 static void setup_planes_for_vactive_by_mask(struct display_configuation_with_meta *display_config, in pmo_dcn42_test_for_pstate_support()
78 for (plane_index = 0; plane_index < display_config->display_config.num_planes; plane_index++) { in pmo_dcn42_test_for_pstate_support()
80 plane = &display_config->display_config.plane_descriptors[plane_index]; in pmo_dcn42_test_for_pstate_support()
85 display_config->stage3.pstate_switch_modes[plane_index] = dml2_pstate_method_vactive;
90 static void reset_display_configuration(struct display_configuation_with_meta *display_config) in pmo_dcn42_initialize()
96 for (stream_index = 0; stream_index < display_config->display_config.num_streams; stream_index++) { in pmo_dcn42_initialize()
97 display_config in pmo_dcn42_initialize()
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H A Ddml2_pmo_dcn4_fams2.h41 const struct display_configuation_with_meta *display_config,
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/
H A Ddml2_top_soc15.c12 static void setup_unoptimized_display_config_with_meta(const struct dml2_instance *dml, struct display_configuation_with_meta *out, const struct dml2_display_cfg *display_config) in setup_unoptimized_display_config_with_meta() argument
14 memcpy(&out->display_config, display_config, sizeof(struct dml2_display_cfg)); in setup_unoptimized_display_config_with_meta()
18 static void setup_speculative_display_config_with_meta(const struct dml2_instance *dml, struct display_configuation_with_meta *out, const struct dml2_display_cfg *display_config) in setup_speculative_display_config_with_meta() argument
21 memcpy(&out->display_config, display_config, sizeof(struct dml2_display_cfg)); in setup_speculative_display_config_with_meta()
32 struct dml2_optimization_stage1_state *state = &params->display_config->stage1; in dml2_top_optimization_init_function_min_clk_for_latency()
41 struct dml2_optimization_stage1_state *state = &params->display_config->stage1; in dml2_top_optimization_test_function_min_clk_for_latency()
50 if (params->display_config->stage1.min_clk_index_for_latency > 0) { in dml2_top_optimization_optimize_function_min_clk_for_latency()
51 copy_display_configuration_with_meta(params->optimized_display_config, params->display_config); in dml2_top_optimization_optimize_function_min_clk_for_latency()
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/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/
H A Ddml21_wrapper.c37 (*dml_ctx)->v21.mode_support.display_config = &(*dml_ctx)->v21.display_config; in dml21_allocate_memory()
38 (*dml_ctx)->v21.mode_programming.display_config = (*dml_ctx)->v21.mode_support.display_config; in dml21_allocate_memory()
85 dst_dml_ctx->v21.mode_support.display_config = &dst_dml_ctx->v21.display_config; in dml21_copy()
86 dst_dml_ctx->v21.mode_programming.display_config = dst_dml_ctx->v21.mode_support.display_config; in dml21_copy()
H A Ddml21_wrapper_fpu.c77 dml_phantom_prog_idx = in_ctx->v21.mode_programming.programming->display_config.num_planes; in dml21_calculate_rq_and_dlg_params()
176 memset(&dml_ctx->v21.display_config, 0, sizeof(struct dml2_display_cfg)); in dml21_check_mode_support()
205 memset(&dml_ctx->v21.display_config, 0, sizeof(struct dml2_display_cfg)); in dml21_mode_check_and_programming()
292 dml_phantom_prog_idx = dml_ctx->v21.mode_programming.programming->display_config.num_planes; in dml21_prepare_mcache_programming()
295 …for (dml_prog_idx = 0; dml_prog_idx < dml_ctx->v21.mode_programming.programming->display_config.nu… in dml21_prepare_mcache_programming()
348 …for (dml_prog_idx = 0; dml_prog_idx < dml_ctx->v21.mode_programming.programming->display_config.nu… in dml21_prepare_mcache_programming()
H A Ddml21_utils.c332 for (dml_stream_index = 0; dml_stream_index < dml_ctx->v21.mode_programming.programming->display_config.num_streams; dml_stream_index++) { in dml21_handle_phantom_streams_planes()
355 for (dml_plane_index = 0; dml_plane_index < dml_ctx->v21.mode_programming.programming->display_config.num_planes; dml_plane_index++) { in dml21_handle_phantom_streams_planes()
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/
H A Ddml2_core_dcn4.c312 memcpy(svp_expanded_display_cfg, &display_cfg->display_config, sizeof(struct dml2_display_cfg)); in expand_implict_subvp()
317 if (!display_cfg->display_config.overrides.enable_subvp_implicit_pmo) in expand_implict_subvp()
326 for (stream_index = 0; stream_index < display_cfg->display_config.num_streams; stream_index++) { in expand_implict_subvp()
327 main_stream = &display_cfg->display_config.stream_descriptors[stream_index]; in expand_implict_subvp()
346 for (plane_index = 0; plane_index < display_cfg->display_config.num_planes; plane_index++) { in expand_implict_subvp()
347 main_plane = &display_cfg->display_config.plane_descriptors[plane_index]; in expand_implict_subvp()
350 main_stream = &display_cfg->display_config.stream_descriptors[main_plane->stream_index]; in expand_implict_subvp()
381 memcpy(&programming->display_config, &display_cfg->display_config, sizeof(struct dml2_display_cfg)); in pack_mode_programming_params_with_implicit_subvp()
384 dml2_core_calcs_get_arb_params(&display_cfg->display_config, in pack_mode_programming_params_with_implicit_subvp()
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H A Ddml2_core_utils.c618 memcpy(svp_expanded_display_cfg, &display_cfg->display_config, sizeof(struct dml2_display_cfg)); in dml2_core_utils_expand_implict_subvp()
623 if (!display_cfg->display_config.overrides.enable_subvp_implicit_pmo) in dml2_core_utils_expand_implict_subvp()
632 for (stream_index = 0; stream_index < display_cfg->display_config.num_streams; stream_index++) { in dml2_core_utils_expand_implict_subvp()
633 main_stream = &display_cfg->display_config.stream_descriptors[stream_index]; in dml2_core_utils_expand_implict_subvp()
652 for (plane_index = 0; plane_index < display_cfg->display_config.num_planes; plane_index++) { in dml2_core_utils_expand_implict_subvp()
653 main_plane = &display_cfg->display_config.plane_descriptors[plane_index]; in dml2_core_utils_expand_implict_subvp()
656 main_stream = &display_cfg->display_config.stream_descriptors[main_plane->stream_index]; in dml2_core_utils_expand_implict_subvp()
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/
H A Ddml2_dpmm_dcn4.c70 if (in_out->display_cfg->display_config.hostvm_enable) in calculate_system_active_minimums()
436 for (i = 0; i < display_cfg->display_config.num_streams; i++) { in map_min_clocks_to_dpm()
454 static bool are_timings_trivially_synchronizable(struct dml2_display_cfg *display_config, int mask) in are_timings_trivially_synchronizable() argument
463 for (i = 0; i < display_config->num_streams; i++) { in are_timings_trivially_synchronizable()
475 …if (memcmp(&display_config->stream_descriptors[remap_array[i - 1]].timing, &display_config->stream… in are_timings_trivially_synchronizable()
483 if (display_config->stream_descriptors[remap_array[i]].timing.drr_config.enabled) { in are_timings_trivially_synchronizable()
502 for (i = 0; i < in_out->programming->display_config.num_streams; i++) { in find_smallest_idle_time_in_vblank_us()
525 if (are_timings_trivially_synchronizable(&in_out->programming->display_config, 0xF)) { in determine_power_management_features_with_vblank_only()
544 for (i = 0; i < in_out->programming->display_config.num_planes; i++) { in get_displays_without_vactive_margin_mask()
559 for (i = 0; i < in_out->programming->display_config.num_planes; i++) { in get_displays_with_fams_mask()
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/linux/arch/arm/mach-davinci/
H A Dda8xx.h74 (struct vpif_display_config *display_config);
H A Dda850.c332 *display_config) in da850_register_vpif_display()
334 da850_vpif_display_dev.dev.platform_data = display_config; in da850_register_vpif_display()
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega12_hwmgr.c1623 if ((hwmgr->display_config->num_display > 1) && in vega12_notify_smc_display_config_after_ps_adjustment()
1624 !hwmgr->display_config->multi_monitor_in_sync && in vega12_notify_smc_display_config_after_ps_adjustment()
1625 !hwmgr->display_config->nb_pstate_switch_disable) in vega12_notify_smc_display_config_after_ps_adjustment()
1630 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; in vega12_notify_smc_display_config_after_ps_adjustment()
1631 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk; in vega12_notify_smc_display_config_after_ps_adjustment()
1632 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega12_notify_smc_display_config_after_ps_adjustment()
2369 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && in vega12_emit_clock_levels()
2370 !hwmgr->display_config->multi_monitor_in_sync) || in vega12_emit_clock_levels()
2372 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; in vega12_emit_clock_levels()
2423 if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config in vega12_apply_clocks_adjust_rules()
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H A Dvega20_hwmgr.c2358 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; in vega20_notify_smc_display_config_after_ps_adjustment()
2359 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk; in vega20_notify_smc_display_config_after_ps_adjustment()
2360 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega20_notify_smc_display_config_after_ps_adjustment()
3710 hwmgr->display_config->num_display, in vega20_display_configuration_changed_task()
3785 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && in vega20_power_gate_uvd()
3786 !hwmgr->display_config->multi_monitor_in_sync) || in vega20_power_gate_uvd()
3788 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; in vega20_power_gate_uvd()
3839 if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100)) in vega20_apply_clocks_adjust_rules()
3840 dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100; in vega20_apply_clocks_adjust_rules()
3847 if (dpm_table->dpm_levels[i].value >= (hwmgr->display_config in vega20_apply_clocks_adjust_rules()
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H A Dsmu7_hwmgr.c3149 const struct amd_pp_display_configuration *cfg = hwmgr->display_config; in smu7_lookup_vddc_from_dispclk()
3448 minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock; in smu7_apply_state_adjust_rules()
3449 minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in smu7_apply_state_adjust_rules()
3479 disable_mclk_switching_for_display = ((1 < hwmgr->display_config->num_display) && in smu7_apply_state_adjust_rules()
3480 !hwmgr->display_config->multi_monitor_in_sync) || in smu7_apply_state_adjust_rules()
3481 (hwmgr->display_config->num_display && in smu7_apply_state_adjust_rules()
3482 smu7_vblank_too_short(hwmgr, hwmgr->display_config->min_vblank_time)); in smu7_apply_state_adjust_rules()
3487 if (hwmgr->display_config->num_display == 0) { in smu7_apply_state_adjust_rules()
3529 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; in smu7_apply_state_adjust_rules()
4223 if (data->display_timing.num_existing_displays != hwmgr->display_config in smu7_find_dpm_states_clocks_in_dpm_table()
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H A Dsmu10_hwmgr.c156 clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; in smu10_init_dynamic_state_adjustment_rule_settings()
587 uint32_t min_sclk = hwmgr->display_config->min_core_set_clock; in smu10_hwmgr_backend_init()
588 uint32_t min_mclk = hwmgr->display_config->min_mem_set_clock/100; in smu10_hwmgr_backend_init()
744 hwmgr->display_config->num_display > 3 ? in smu10_dpm_force_dpm_level()
H A Dvega10_hwmgr.c3324 minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock; in vega10_apply_state_adjust_rules()
3325 minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega10_apply_state_adjust_rules()
3365 if (hwmgr->display_config->num_display == 0) in vega10_apply_state_adjust_rules()
3368 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && in vega10_apply_state_adjust_rules()
3369 !hwmgr->display_config->multi_monitor_in_sync) || in vega10_apply_state_adjust_rules()
3401 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; in vega10_apply_state_adjust_rules()
3471 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) in vega10_find_dpm_states_clocks_in_dpm_table()
4106 if ((hwmgr->display_config->num_display > 1) && in vega10_notify_smc_display_config_after_ps_adjustment()
4107 !hwmgr->display_config->multi_monitor_in_sync && in vega10_notify_smc_display_config_after_ps_adjustment()
4108 !hwmgr->display_config in vega10_notify_smc_display_config_after_ps_adjustment()
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H A Dsmu8_hwmgr.c672 clock = hwmgr->display_config->min_core_set_clock; in smu8_init_power_gate_state()
730 uint32_t clks = hwmgr->display_config->min_core_set_clock_in_sr; in smu8_update_sclk_limit()
1054 clocks.memoryClock = hwmgr->display_config->min_mem_set_clock != 0 ? in smu8_disable_dpm_tasks()
1055 hwmgr->display_config->min_mem_set_clock : in smu8_disable_dpm_tasks()
1063 || (hwmgr->display_config->num_display >= 3); in smu8_power_off_asic()
/linux/drivers/gpu/drm/amd/pm/powerplay/
H A Damd_powerplay.c60 hwmgr->display_config = &adev->pm.pm_display_cfg; in amd_powerplay_create()
1015 const struct amd_pp_display_configuration *display_config) in pp_display_configuration_change()
1022 phm_store_dal_configuration_data(hwmgr, display_config);
1012 pp_display_configuration_change(void * handle,const struct amd_pp_display_configuration * display_config) pp_display_configuration_change() argument
/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dvegam_smumgr.c839 data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr; in vegam_populate_single_graphic_level()
843 hwmgr->display_config->min_core_set_clock_in_sr); in vegam_populate_single_graphic_level()
1013 data->display_timing.num_existing_displays = hwmgr->display_config->num_display; in vegam_populate_single_memory_level()
1014 data->display_timing.vrefresh = hwmgr->display_config->vrefresh; in vegam_populate_single_memory_level()
H A Dfiji_smumgr.c974 data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr; in fiji_populate_single_graphic_level()
978 hwmgr->display_config->min_core_set_clock_in_sr); in fiji_populate_single_graphic_level()
1199 data->display_timing.num_existing_displays = hwmgr->display_config->num_display; in fiji_populate_single_memory_level()
1200 data->display_timing.vrefresh = hwmgr->display_config->vrefresh; in fiji_populate_single_memory_level()
H A Dpolaris10_smumgr.c993 data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr; in polaris10_populate_single_graphic_level()
997 hwmgr->display_config->min_core_set_clock_in_sr); in polaris10_populate_single_graphic_level()
1188 data->display_timing.num_existing_displays = hwmgr->display_config->num_display; in polaris10_populate_single_memory_level()
1189 data->display_timing.vrefresh = hwmgr->display_config->vrefresh; in polaris10_populate_single_memory_level()
H A Diceland_smumgr.c932 hwmgr->display_config->min_core_set_clock_in_sr; in iceland_populate_single_graphic_level()
1282 data->display_timing.num_existing_displays = hwmgr->display_config->num_display; in iceland_populate_single_memory_level()
1283 data->display_timing.vrefresh = hwmgr->display_config->vrefresh; in iceland_populate_single_memory_level()
H A Dtonga_smumgr.c659 hwmgr->display_config->min_core_set_clock_in_sr; in tonga_populate_single_graphic_level()
1016 data->display_timing.num_existing_displays = hwmgr->display_config->num_display; in tonga_populate_single_memory_level()
1017 data->display_timing.vrefresh = hwmgr->display_config->vrefresh; in tonga_populate_single_memory_level()
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/
H A Damdgpu_smu.h711 struct amd_pp_display_configuration *display_config; member

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