Searched refs:display_config (Results 1 – 14 of 14) sorted by relevance
74 (struct vpif_display_config *display_config);
332 *display_config) in da850_register_vpif_display()334 da850_vpif_display_dev.dev.platform_data = display_config; in da850_register_vpif_display()
1623 if ((hwmgr->display_config->num_display > 1) && in vega12_notify_smc_display_config_after_ps_adjustment()1624 !hwmgr->display_config->multi_monitor_in_sync && in vega12_notify_smc_display_config_after_ps_adjustment()1625 !hwmgr->display_config->nb_pstate_switch_disable) in vega12_notify_smc_display_config_after_ps_adjustment()1630 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; in vega12_notify_smc_display_config_after_ps_adjustment()1631 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk; in vega12_notify_smc_display_config_after_ps_adjustment()1632 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega12_notify_smc_display_config_after_ps_adjustment()2366 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && in vega12_apply_clocks_adjust_rules()2367 !hwmgr->display_config->multi_monitor_in_sync) || in vega12_apply_clocks_adjust_rules()2369 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; in vega12_apply_clocks_adjust_rules()2420 if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100)) in vega12_apply_clocks_adjust_rules()[all …]
2358 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; in vega20_notify_smc_display_config_after_ps_adjustment()2359 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk; in vega20_notify_smc_display_config_after_ps_adjustment()2360 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega20_notify_smc_display_config_after_ps_adjustment()3673 hwmgr->display_config->num_display, in vega20_display_configuration_changed_task()3748 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && in vega20_apply_clocks_adjust_rules()3749 !hwmgr->display_config->multi_monitor_in_sync) || in vega20_apply_clocks_adjust_rules()3751 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; in vega20_apply_clocks_adjust_rules()3802 if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100)) in vega20_apply_clocks_adjust_rules()3803 dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100; in vega20_apply_clocks_adjust_rules()3810 if (dpm_table->dpm_levels[i].value >= (hwmgr->display_config->min_mem_set_clock / 100)) { in vega20_apply_clocks_adjust_rules()[all …]
3328 minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock; in vega10_apply_state_adjust_rules()3329 minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega10_apply_state_adjust_rules()3369 if (hwmgr->display_config->num_display == 0) in vega10_apply_state_adjust_rules()3372 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && in vega10_apply_state_adjust_rules()3373 !hwmgr->display_config->multi_monitor_in_sync) || in vega10_apply_state_adjust_rules()3405 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; in vega10_apply_state_adjust_rules()3475 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) in vega10_find_dpm_states_clocks_in_dpm_table()4110 if ((hwmgr->display_config->num_display > 1) && in vega10_notify_smc_display_config_after_ps_adjustment()4111 !hwmgr->display_config->multi_monitor_in_sync && in vega10_notify_smc_display_config_after_ps_adjustment()4112 !hwmgr->display_config->nb_pstate_switch_disable) in vega10_notify_smc_display_config_after_ps_adjustment()[all …]
3356 minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock; in smu7_apply_state_adjust_rules()3357 minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in smu7_apply_state_adjust_rules()3387 disable_mclk_switching_for_display = ((1 < hwmgr->display_config->num_display) && in smu7_apply_state_adjust_rules()3388 !hwmgr->display_config->multi_monitor_in_sync) || in smu7_apply_state_adjust_rules()3389 (hwmgr->display_config->num_display && in smu7_apply_state_adjust_rules()3390 smu7_vblank_too_short(hwmgr, hwmgr->display_config->min_vblank_time)); in smu7_apply_state_adjust_rules()3395 if (hwmgr->display_config->num_display == 0) { in smu7_apply_state_adjust_rules()3437 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; in smu7_apply_state_adjust_rules()4131 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) in smu7_find_dpm_states_clocks_in_dpm_table()4588 …display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (hwmgr->display_config->nu… in smu7_program_display_gap()[all …]
711 clock = hwmgr->display_config->min_core_set_clock; in smu8_update_sclk_limit()769 uint32_t clks = hwmgr->display_config->min_core_set_clock_in_sr; in smu8_set_deep_sleep_sclk_threshold()1093 clocks.memoryClock = hwmgr->display_config->min_mem_set_clock != 0 ? in smu8_apply_state_adjust_rules()1094 hwmgr->display_config->min_mem_set_clock : in smu8_apply_state_adjust_rules()1102 || (hwmgr->display_config->num_display >= 3); in smu8_apply_state_adjust_rules()
60 hwmgr->display_config = &adev->pm.pm_display_cfg; in amd_powerplay_create()1027 const struct amd_pp_display_configuration *display_config) in pp_display_configuration_change() argument1034 phm_store_dal_configuration_data(hwmgr, display_config); in pp_display_configuration_change()
839 data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr; in vegam_populate_single_graphic_level()843 hwmgr->display_config->min_core_set_clock_in_sr); in vegam_populate_single_graphic_level()1013 data->display_timing.num_existing_displays = hwmgr->display_config->num_display; in vegam_populate_single_memory_level()1014 data->display_timing.vrefresh = hwmgr->display_config->vrefresh; in vegam_populate_single_memory_level()
974 data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr; in fiji_populate_single_graphic_level()978 hwmgr->display_config->min_core_set_clock_in_sr); in fiji_populate_single_graphic_level()1199 data->display_timing.num_existing_displays = hwmgr->display_config->num_display; in fiji_populate_single_memory_level()1200 data->display_timing.vrefresh = hwmgr->display_config->vrefresh; in fiji_populate_single_memory_level()
932 hwmgr->display_config->min_core_set_clock_in_sr; in iceland_populate_single_graphic_level()1282 data->display_timing.num_existing_displays = hwmgr->display_config->num_display; in iceland_populate_single_memory_level()1283 data->display_timing.vrefresh = hwmgr->display_config->vrefresh; in iceland_populate_single_memory_level()
1236 data->display_timing.num_existing_displays = hwmgr->display_config->num_display; in ci_populate_single_memory_level()1237 data->display_timing.vrefresh = hwmgr->display_config->vrefresh; in ci_populate_single_memory_level()
1383 smu->display_config = &adev->pm.pm_display_cfg; in smu_sw_init()2288 const struct amd_pp_display_configuration *display_config) in smu_display_configuration_change() argument2295 if (!display_config) in smu_display_configuration_change()2299 display_config->min_dcef_deep_sleep_set_clk / 100); in smu_display_configuration_change()
1866 smu->display_config->num_display, in navi10_display_config_changed()2136 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk; in navi10_notify_smc_display_config()2137 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk; in navi10_notify_smc_display_config()2138 min_clocks.memory_clock = smu->display_config->min_mem_set_clock; in navi10_notify_smc_display_config()