| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/ |
| H A D | dml2_internal_shared_types.h | 358 struct dml2_display_cfg display_config; member
529 const struct dml2_display_cfg *display_config; member
552 const struct display_configuation_with_meta *display_config; member
803 const struct dml2_display_cfg *display_config; member
898 struct display_configuation_with_meta *display_config; member
904 struct display_configuation_with_meta *display_config; member
911 struct display_configuation_with_meta *display_config; member
917 const struct display_configuation_with_meta *display_config; // Initial Display Configuration member
972 const struct dml2_display_cfg *display_config; member
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/ |
| H A D | dml2_dpmm_dcn4.c | 70 if (in_out->display_cfg->display_config.hostvm_enable) in calculate_system_active_minimums()
416 for (i = 0; i < display_cfg->display_config.num_streams; i++) { in map_min_clocks_to_dpm()
434 static bool are_timings_trivially_synchronizable(struct dml2_display_cfg *display_config, int mask) in are_timings_trivially_synchronizable() argument
443 for (i = 0; i < display_config->num_streams; i++) { in are_timings_trivially_synchronizable()
455 …if (memcmp(&display_config->stream_descriptors[remap_array[i - 1]].timing, &display_config->stream… in are_timings_trivially_synchronizable()
463 if (display_config->stream_descriptors[remap_array[i]].timing.drr_config.enabled) { in are_timings_trivially_synchronizable()
482 for (i = 0; i < in_out->programming->display_config.num_streams; i++) { in find_smallest_idle_time_in_vblank_us()
505 if (are_timings_trivially_synchronizable(&in_out->programming->display_config, 0xF)) { in determine_power_management_features_with_vblank_only()
524 for (i = 0; i < in_out->programming->display_config.num_planes; i++) { in get_displays_without_vactive_margin_mask()
538 for (i = 0; i < in_out->programming->display_config.num_planes; i++) { in get_displays_with_fams_mask()
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| /linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| H A D | vega12_hwmgr.c | 1623 if ((hwmgr->display_config->num_display > 1) && in vega12_notify_smc_display_config_after_ps_adjustment()
1624 !hwmgr->display_config->multi_monitor_in_sync && in vega12_notify_smc_display_config_after_ps_adjustment()
1625 !hwmgr->display_config->nb_pstate_switch_disable) in vega12_notify_smc_display_config_after_ps_adjustment()
1630 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; in vega12_notify_smc_display_config_after_ps_adjustment()
1631 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk; in vega12_notify_smc_display_config_after_ps_adjustment()
1632 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega12_notify_smc_display_config_after_ps_adjustment()
2384 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && in vega12_apply_clocks_adjust_rules()
2385 !hwmgr->display_config->multi_monitor_in_sync) || in vega12_apply_clocks_adjust_rules()
2387 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; in vega12_apply_clocks_adjust_rules()
2438 if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100)) in vega12_apply_clocks_adjust_rules()
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| H A D | vega20_hwmgr.c | 2358 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; in vega20_notify_smc_display_config_after_ps_adjustment()
2359 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk; in vega20_notify_smc_display_config_after_ps_adjustment()
2360 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega20_notify_smc_display_config_after_ps_adjustment()
3726 hwmgr->display_config->num_display, in vega20_display_configuration_changed_task()
3801 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && in vega20_apply_clocks_adjust_rules()
3802 !hwmgr->display_config->multi_monitor_in_sync) || in vega20_apply_clocks_adjust_rules()
3804 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; in vega20_apply_clocks_adjust_rules()
3855 if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100)) in vega20_apply_clocks_adjust_rules()
3856 dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100; in vega20_apply_clocks_adjust_rules()
3863 if (dpm_table->dpm_levels[i].value >= (hwmgr->display_config->min_mem_set_clock / 100)) { in vega20_apply_clocks_adjust_rules()
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| H A D | smu10_hwmgr.c | 193 clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; in smu10_set_clock_limit()
627 uint32_t min_sclk = hwmgr->display_config->min_core_set_clock; in smu10_dpm_force_dpm_level()
628 uint32_t min_mclk = hwmgr->display_config->min_mem_set_clock/100; in smu10_dpm_force_dpm_level()
784 hwmgr->display_config->num_display > 3 ? in smu10_dpm_force_dpm_level()
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| H A D | smu7_hwmgr.c | 3356 minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock; in smu7_apply_state_adjust_rules()
3357 minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in smu7_apply_state_adjust_rules()
3387 disable_mclk_switching_for_display = ((1 < hwmgr->display_config->num_display) && in smu7_apply_state_adjust_rules()
3388 !hwmgr->display_config->multi_monitor_in_sync) || in smu7_apply_state_adjust_rules()
3389 (hwmgr->display_config->num_display && in smu7_apply_state_adjust_rules()
3390 smu7_vblank_too_short(hwmgr, hwmgr->display_config->min_vblank_time)); in smu7_apply_state_adjust_rules()
3395 if (hwmgr->display_config->num_display == 0) { in smu7_apply_state_adjust_rules()
3437 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; in smu7_apply_state_adjust_rules()
4131 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) in smu7_find_dpm_states_clocks_in_dpm_table()
4588 …display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (hwmgr->display_config->nu… in smu7_program_display_gap()
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| H A D | vega10_hwmgr.c | 3327 minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock; in vega10_apply_state_adjust_rules()
3328 minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega10_apply_state_adjust_rules()
3368 if (hwmgr->display_config->num_display == 0) in vega10_apply_state_adjust_rules()
3371 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && in vega10_apply_state_adjust_rules()
3372 !hwmgr->display_config->multi_monitor_in_sync) || in vega10_apply_state_adjust_rules()
3404 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; in vega10_apply_state_adjust_rules()
3474 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) in vega10_find_dpm_states_clocks_in_dpm_table()
4109 if ((hwmgr->display_config->num_display > 1) && in vega10_notify_smc_display_config_after_ps_adjustment()
4110 !hwmgr->display_config->multi_monitor_in_sync && in vega10_notify_smc_display_config_after_ps_adjustment()
4111 !hwmgr->display_config->nb_pstate_switch_disable) in vega10_notify_smc_display_config_after_ps_adjustment()
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| H A D | smu8_hwmgr.c | 710 clock = hwmgr->display_config->min_core_set_clock; in smu8_update_sclk_limit()
768 uint32_t clks = hwmgr->display_config->min_core_set_clock_in_sr; in smu8_set_deep_sleep_sclk_threshold()
1092 clocks.memoryClock = hwmgr->display_config->min_mem_set_clock != 0 ? in smu8_apply_state_adjust_rules()
1093 hwmgr->display_config->min_mem_set_clock : in smu8_apply_state_adjust_rules()
1101 || (hwmgr->display_config->num_display >= 3); in smu8_apply_state_adjust_rules()
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| /linux/arch/arm/mach-davinci/ |
| H A D | da8xx.h | 74 (struct vpif_display_config *display_config);
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| H A D | da850.c | 332 *display_config) in da850_register_vpif_display()
334 da850_vpif_display_dev.dev.platform_data = display_config; in da850_register_vpif_display()
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| /linux/drivers/gpu/drm/amd/pm/powerplay/ |
| H A D | amd_powerplay.c | 60 hwmgr->display_config = &adev->pm.pm_display_cfg; in amd_powerplay_create()
1012 const struct amd_pp_display_configuration *display_config) in pp_display_configuration_change() argument
1019 phm_store_dal_configuration_data(hwmgr, display_config); in pp_display_configuration_change()
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| /linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| H A D | vegam_smumgr.c | 839 data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr; in vegam_populate_single_graphic_level()
843 hwmgr->display_config->min_core_set_clock_in_sr); in vegam_populate_single_graphic_level()
1013 data->display_timing.num_existing_displays = hwmgr->display_config->num_display; in vegam_populate_single_memory_level()
1014 data->display_timing.vrefresh = hwmgr->display_config->vrefresh; in vegam_populate_single_memory_level()
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| H A D | fiji_smumgr.c | 974 data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr; in fiji_populate_single_graphic_level()
978 hwmgr->display_config->min_core_set_clock_in_sr); in fiji_populate_single_graphic_level()
1199 data->display_timing.num_existing_displays = hwmgr->display_config->num_display; in fiji_populate_single_memory_level()
1200 data->display_timing.vrefresh = hwmgr->display_config->vrefresh; in fiji_populate_single_memory_level()
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| H A D | polaris10_smumgr.c | 993 data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr; in polaris10_populate_single_graphic_level()
997 hwmgr->display_config->min_core_set_clock_in_sr); in polaris10_populate_single_graphic_level()
1188 data->display_timing.num_existing_displays = hwmgr->display_config->num_display; in polaris10_populate_single_memory_level()
1189 data->display_timing.vrefresh = hwmgr->display_config->vrefresh; in polaris10_populate_single_memory_level()
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| H A D | iceland_smumgr.c | 932 hwmgr->display_config->min_core_set_clock_in_sr; in iceland_populate_single_graphic_level()
1282 data->display_timing.num_existing_displays = hwmgr->display_config->num_display; in iceland_populate_single_memory_level()
1283 data->display_timing.vrefresh = hwmgr->display_config->vrefresh; in iceland_populate_single_memory_level()
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| H A D | tonga_smumgr.c | 659 hwmgr->display_config->min_core_set_clock_in_sr; in tonga_populate_single_graphic_level()
1016 data->display_timing.num_existing_displays = hwmgr->display_config->num_display; in tonga_populate_single_memory_level()
1017 data->display_timing.vrefresh = hwmgr->display_config->vrefresh; in tonga_populate_single_memory_level()
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| H A D | ci_smumgr.c | 1236 data->display_timing.num_existing_displays = hwmgr->display_config->num_display; in ci_populate_single_memory_level()
1237 data->display_timing.vrefresh = hwmgr->display_config->vrefresh; in ci_populate_single_memory_level()
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| /linux/drivers/gpu/drm/amd/pm/swsmu/ |
| H A D | amdgpu_smu.c | 1373 smu->display_config = &adev->pm.pm_display_cfg; in smu_sw_init()
2275 const struct amd_pp_display_configuration *display_config) in smu_display_configuration_change() argument
2282 if (!display_config) in smu_display_configuration_change()
2286 display_config->min_dcef_deep_sleep_set_clk / 100); in smu_display_configuration_change()
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| H A D | navi10_ppt.c | 1610 smu->display_config->num_display, in navi10_display_config_changed()
1881 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk; in navi10_notify_smc_display_config()
1882 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk; in navi10_notify_smc_display_config()
1883 min_clocks.memory_clock = smu->display_config->min_mem_set_clock; in navi10_notify_smc_display_config()
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| H A D | sienna_cichlid_ppt.c | 1525 smu->display_config->num_display, in sienna_cichlid_display_config_changed()
1797 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk; in sienna_cichlid_notify_smc_display_config()
1798 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk; in sienna_cichlid_notify_smc_display_config()
1799 min_clocks.memory_clock = smu->display_config->min_mem_set_clock; in sienna_cichlid_notify_smc_display_config()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/ |
| H A D | dml21_translation_helper.c | 731 struct dml2_display_cfg *dml_dispcfg = &dml_ctx->v21.display_config; in dml21_map_dc_state_into_dml_display_cfg()
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| /linux/drivers/gpu/drm/amd/pm/swsmu/inc/ |
| H A D | amdgpu_smu.h | 709 struct amd_pp_display_configuration *display_config; member
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/ |
| H A D | dml2_core_dcn4_calcs.c | 12786 fams2_global_config->num_streams = display_cfg->display_config.num_streams; in dml2_core_calcs_get_global_fams2_programming()
12797 …const struct dml2_plane_parameters *plane_descriptor = &display_cfg->display_config.plane_descript… in dml2_core_calcs_get_stream_fams2_programming()
12798 …const struct dml2_stream_parameters *stream_descriptor = &display_cfg->display_config.stream_descr… in dml2_core_calcs_get_stream_fams2_programming()
12806 if (display_cfg->display_config.overrides.all_streams_blanked) { in dml2_core_calcs_get_stream_fams2_programming()
12835 for (i = 0; i < display_cfg->display_config.num_planes; i++) { in dml2_core_calcs_get_stream_fams2_programming()
12837 …if (display_cfg->display_config.plane_descriptors[i].stream_index == plane_descriptor->stream_inde… in dml2_core_calcs_get_stream_fams2_programming()
12879 base_programming->config.bits.clamp_vtotal_min = display_cfg->display_config.num_streams == 1; in dml2_core_calcs_get_stream_fams2_programming()
13076 for (k = 0; k < out->display_config.num_planes; k++) { in dml2_core_calcs_get_informative()
13151 for (k = 0; k < out->display_config.num_planes; ++k) { in dml2_core_calcs_get_informative()
13235 for (k = 0; k < out->display_config.num_planes; k++) { in dml2_core_calcs_get_informative()
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