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Searched refs:display (Results 1 – 25 of 731) sorted by relevance

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/linux/drivers/gpu/drm/i915/display/
H A Dintel_display_irq.c33 static void irq_reset(struct intel_display *display, struct i915_irq_regs regs) in irq_reset() argument
35 intel_de_write(display, regs.imr, 0xffffffff); in irq_reset()
36 intel_de_posting_read(display, regs.imr); in irq_reset()
38 intel_de_write(display, regs.ier, 0); in irq_reset()
41 intel_de_write(display, regs.iir, 0xffffffff); in irq_reset()
42 intel_de_posting_read(display, regs.iir); in irq_reset()
43 intel_de_write(display, regs.iir, 0xffffffff); in irq_reset()
44 intel_de_posting_read(display, regs.iir); in irq_reset()
50 static void assert_iir_is_zero(struct intel_display *display, i915_reg_t reg) in assert_iir_is_zero() argument
52 u32 val = intel_de_read(display, reg); in assert_iir_is_zero()
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H A Dintel_display_power_well.c45 static enum skl_power_gate pw_idx_to_pg(struct intel_display *display, int pw_idx) in pw_idx_to_pg() argument
47 int pw1_idx = DISPLAY_VER(display) >= 11 ? ICL_PW_CTL_IDX_PW_1 : SKL_PW_CTL_IDX_PW_1; in pw_idx_to_pg()
67 void (*sync_hw)(struct intel_display *display,
74 void (*enable)(struct intel_display *display,
80 void (*disable)(struct intel_display *display,
83 bool (*is_enabled)(struct intel_display *display,
94 lookup_power_well(struct intel_display *display, in lookup_power_well() argument
99 for_each_power_well(display, power_well) in lookup_power_well()
110 drm_WARN(display->drm, 1, in lookup_power_well()
113 return &display->power.domains.power_wells[0]; in lookup_power_well()
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H A Dintel_cdclk.c161 void (*get_cdclk)(struct intel_display *display,
163 void (*set_cdclk)(struct intel_display *display,
170 void intel_cdclk_get_cdclk(struct intel_display *display, in intel_cdclk_get_cdclk() argument
173 display->funcs.cdclk->get_cdclk(display, cdclk_config); in intel_cdclk_get_cdclk()
176 static void intel_cdclk_set_cdclk(struct intel_display *display, in intel_cdclk_set_cdclk() argument
180 display->funcs.cdclk->set_cdclk(display, cdclk_config, pipe); in intel_cdclk_set_cdclk()
185 struct intel_display *display = to_intel_display(state); in intel_cdclk_modeset_calc_cdclk() local
187 return display->funcs.cdclk->modeset_calc_cdclk(state); in intel_cdclk_modeset_calc_cdclk()
190 static u8 intel_cdclk_calc_voltage_level(struct intel_display *display, in intel_cdclk_calc_voltage_level() argument
193 return display->funcs.cdclk->calc_voltage_level(cdclk); in intel_cdclk_calc_voltage_level()
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H A Dintel_gmbus.c54 struct intel_display *display; member
155 static const struct gmbus_pin *get_gmbus_pin(struct intel_display *display, in get_gmbus_pin() argument
161 if (INTEL_PCH_TYPE(display) >= PCH_MTL) { in get_gmbus_pin()
164 } else if (INTEL_PCH_TYPE(display) >= PCH_DG2) { in get_gmbus_pin()
167 } else if (INTEL_PCH_TYPE(display) >= PCH_DG1) { in get_gmbus_pin()
170 } else if (INTEL_PCH_TYPE(display) >= PCH_ICP) { in get_gmbus_pin()
173 } else if (HAS_PCH_CNP(display)) { in get_gmbus_pin()
176 } else if (display->platform.geminilake || display->platform.broxton) { in get_gmbus_pin()
179 } else if (DISPLAY_VER(display) == 9) { in get_gmbus_pin()
182 } else if (display->platform.broadwell) { in get_gmbus_pin()
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H A Dintel_dmc.c65 struct intel_display *display; member
87 static struct intel_dmc *display_to_dmc(struct intel_display *display) in display_to_dmc() argument
89 return display->dmc.dmc; in display_to_dmc()
92 static const char *dmc_firmware_param(struct intel_display *display) in dmc_firmware_param() argument
94 const char *p = display->params.dmc_firmware_path; in dmc_firmware_param()
99 static bool dmc_firmware_param_disabled(struct intel_display *display) in dmc_firmware_param_disabled() argument
101 const char *p = dmc_firmware_param(display); in dmc_firmware_param_disabled()
188 static const char *dmc_firmware_default(struct intel_display *display, u32 *size) in dmc_firmware_default() argument
193 if (DISPLAY_VERx100(display) == 3500) { in dmc_firmware_default()
196 } else if (DISPLAY_VERx100(display) == 3002) { in dmc_firmware_default()
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H A Dvlv_dsi.c91 struct intel_display *display = to_intel_display(&intel_dsi->base); in vlv_dsi_wait_for_fifo_empty() local
97 if (intel_de_wait_for_set_ms(display, MIPI_GEN_FIFO_STAT(display, port), in vlv_dsi_wait_for_fifo_empty()
99 drm_err(display->drm, "DPI FIFOs are not empty\n"); in vlv_dsi_wait_for_fifo_empty()
102 static void write_data(struct intel_display *display, in write_data() argument
114 intel_de_write(display, reg, val); in write_data()
118 static void read_data(struct intel_display *display, in read_data() argument
125 u32 val = intel_de_read(display, reg); in read_data()
137 struct intel_display *display = to_intel_display(&intel_dsi->base); in intel_dsi_host_transfer() local
152 data_reg = MIPI_LP_GEN_DATA(display, port); in intel_dsi_host_transfer()
154 ctrl_reg = MIPI_LP_GEN_CTRL(display, port); in intel_dsi_host_transfer()
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H A Dintel_fbc.c96 struct intel_display *display; member
130 static struct intel_fbc *intel_fbc_for_pipe(struct intel_display *display, enum pipe pipe) in intel_fbc_for_pipe() argument
132 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); in intel_fbc_for_pipe()
137 if (drm_WARN_ON(display->drm, !primary)) in intel_fbc_for_pipe()
173 static unsigned int skl_fbc_min_cfb_stride(struct intel_display *display, in skl_fbc_min_cfb_stride() argument
187 if (DISPLAY_VER(display) >= 11) in skl_fbc_min_cfb_stride()
201 static unsigned int _intel_fbc_cfb_stride(struct intel_display *display, in _intel_fbc_cfb_stride() argument
210 if (DISPLAY_VER(display) >= 9) in _intel_fbc_cfb_stride()
211 return max(ALIGN(stride, 512), skl_fbc_min_cfb_stride(display, cpp, width)); in _intel_fbc_cfb_stride()
218 struct intel_display *display = to_intel_display(plane_state); in intel_fbc_cfb_stride() local
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H A Dintel_vrr.c35 struct intel_display *display = to_intel_display(connector); in intel_vrr_is_capable() local
39 if (!HAS_VRR(display)) in intel_vrr_is_capable()
98 static int intel_vrr_extra_vblank_delay(struct intel_display *display) in intel_vrr_extra_vblank_delay() argument
106 return DISPLAY_VER(display) < 13 ? 1 : 0; in intel_vrr_extra_vblank_delay()
109 static int intel_vrr_vmin_flipline_offset(struct intel_display *display) in intel_vrr_vmin_flipline_offset() argument
119 return DISPLAY_VER(display) < 13 ? 1 : 0; in intel_vrr_vmin_flipline_offset()
177 struct intel_display *display = to_intel_display(crtc_state); in is_cmrr_frac_required() local
182 if (!HAS_CMRR(display) || true) in is_cmrr_frac_required()
263 struct intel_display *display = to_intel_display(crtc_state); in intel_vrr_hw_value() local
269 if (DISPLAY_VER(display) >= 13) in intel_vrr_hw_value()
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H A Dvlv_dsi_regs.h14 #define _MIPI_MMIO_BASE(display) ((display)->dsi.mmio_base) argument
97 #define MIPI_DEVICE_READY(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DEVICE_R… argument
107 #define MIPI_INTR_STAT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_STAT,… argument
110 #define MIPI_INTR_EN(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_EN, _MI… argument
146 #define MIPI_DSI_FUNC_PRG(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DSI_FUNC… argument
169 #define MIPI_HS_TX_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_TX_T… argument
174 #define MIPI_LP_RX_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_RX_T… argument
179 #define MIPI_TURN_AROUND_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_T… argument
184 #define MIPI_DEVICE_RESET_TIMER(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DE… argument
189 #define MIPI_DPI_RESOLUTION(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPI_RE… argument
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H A Dintel_crt.c91 bool intel_crt_port_enabled(struct intel_display *display, in intel_crt_port_enabled() argument
96 val = intel_de_read(display, adpa_reg); in intel_crt_port_enabled()
99 if (HAS_PCH_CPT(display)) in intel_crt_port_enabled()
110 struct intel_display *display = to_intel_display(encoder); in intel_crt_get_hw_state() local
115 wakeref = intel_display_power_get_if_enabled(display, in intel_crt_get_hw_state()
120 ret = intel_crt_port_enabled(display, crt->adpa_reg, pipe); in intel_crt_get_hw_state()
122 intel_display_power_put(display, encoder->power_domain, wakeref); in intel_crt_get_hw_state()
129 struct intel_display *display = to_intel_display(encoder); in intel_crt_get_flags() local
133 tmp = intel_de_read(display, crt->adpa_reg); in intel_crt_get_flags()
178 struct intel_display *display = to_intel_display(encoder); in intel_crt_set_dpms() local
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H A Dintel_lpe_audio.c79 #define HAS_LPE_AUDIO(display) ((display)->audio.lpe.platdev) argument
82 lpe_audio_platdev_create(struct intel_display *display) in lpe_audio_platdev_create() argument
84 struct pci_dev *pdev = to_pci_dev(display->drm->dev); in lpe_audio_platdev_create()
100 rsc[0].start = display->audio.lpe.irq; in lpe_audio_platdev_create()
101 rsc[0].end = display->audio.lpe.irq; in lpe_audio_platdev_create()
112 pinfo.parent = display->drm->dev; in lpe_audio_platdev_create()
121 pdata->num_pipes = INTEL_NUM_PIPES(display); in lpe_audio_platdev_create()
122 pdata->num_ports = display->platform.cherryview ? 3 : 2; /* B,C,D or B,C */ in lpe_audio_platdev_create()
133 drm_err(display->drm, in lpe_audio_platdev_create()
143 static void lpe_audio_platdev_destroy(struct intel_display *display) in lpe_audio_platdev_destroy() argument
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H A Dintel_psr.c266 struct intel_display *display = to_intel_display(intel_dp); in panel_replay_global_enabled() local
269 display->params.enable_panel_replay; in panel_replay_global_enabled()
274 struct intel_display *display = to_intel_display(intel_dp); in psr_irq_psr_error_bit_get() local
276 return DISPLAY_VER(display) >= 12 ? TGL_PSR_ERROR : in psr_irq_psr_error_bit_get()
282 struct intel_display *display = to_intel_display(intel_dp); in psr_irq_post_exit_bit_get() local
284 return DISPLAY_VER(display) >= 12 ? TGL_PSR_POST_EXIT : in psr_irq_post_exit_bit_get()
290 struct intel_display *display = to_intel_display(intel_dp); in psr_irq_pre_entry_bit_get() local
292 return DISPLAY_VER(display) >= 12 ? TGL_PSR_PRE_ENTRY : in psr_irq_pre_entry_bit_get()
298 struct intel_display *display = to_intel_display(intel_dp); in psr_irq_mask_get() local
300 return DISPLAY_VER(display) >= 12 ? TGL_PSR_MASK : in psr_irq_mask_get()
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H A Dintel_bw.c73 static int dg1_mchbar_read_qgv_point_info(struct intel_display *display, in dg1_mchbar_read_qgv_point_info() argument
77 struct intel_uncore *uncore = to_intel_uncore(display->drm); in dg1_mchbar_read_qgv_point_info()
109 static int icl_pcode_read_qgv_point_info(struct intel_display *display, in icl_pcode_read_qgv_point_info() argument
117 ret = intel_pcode_read(display->drm, ICL_PCODE_MEM_SUBSYSYSTEM_INFO | in icl_pcode_read_qgv_point_info()
124 sp->dclk = DIV_ROUND_UP((16667 * dclk) + (DISPLAY_VER(display) >= 12 ? 500 : 0), in icl_pcode_read_qgv_point_info()
137 static int adls_pcode_read_psf_gv_point_info(struct intel_display *display, in adls_pcode_read_psf_gv_point_info() argument
144 ret = intel_pcode_read(display->drm, ICL_PCODE_MEM_SUBSYSYSTEM_INFO | in adls_pcode_read_psf_gv_point_info()
157 static u16 icl_qgv_points_mask(struct intel_display *display) in icl_qgv_points_mask() argument
159 unsigned int num_psf_gv_points = display->bw.max[0].num_psf_gv_points; in icl_qgv_points_mask()
160 unsigned int num_qgv_points = display->bw.max[0].num_qgv_points; in icl_qgv_points_mask()
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H A Dintel_hdcp.c49 struct intel_display *display = to_intel_display(encoder); in intel_hdcp_adjust_hdcp_line_rekeying() local
57 if (DISPLAY_VER(display) >= 30) { in intel_hdcp_adjust_hdcp_line_rekeying()
58 rekey_reg = TRANS_DDI_FUNC_CTL(display, hdcp->cpu_transcoder); in intel_hdcp_adjust_hdcp_line_rekeying()
60 } else if (IS_DISPLAY_VERx100_STEP(display, 1401, STEP_B0, STEP_FOREVER) || in intel_hdcp_adjust_hdcp_line_rekeying()
61 IS_DISPLAY_VERx100_STEP(display, 2000, STEP_B0, STEP_FOREVER)) { in intel_hdcp_adjust_hdcp_line_rekeying()
62 rekey_reg = TRANS_DDI_FUNC_CTL(display, hdcp->cpu_transcoder); in intel_hdcp_adjust_hdcp_line_rekeying()
64 } else if (IS_DISPLAY_VERx100_STEP(display, 1400, STEP_D0, STEP_FOREVER)) { in intel_hdcp_adjust_hdcp_line_rekeying()
65 rekey_reg = CHICKEN_TRANS(display, hdcp->cpu_transcoder); in intel_hdcp_adjust_hdcp_line_rekeying()
70 intel_de_rmw(display, rekey_reg, rekey_bit, enable ? 0 : rekey_bit); in intel_hdcp_adjust_hdcp_line_rekeying()
115 struct intel_display *display = to_intel_display(state); in intel_hdcp_required_content_stream() local
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H A Dintel_opregion.c259 struct intel_display *display; member
275 static int check_swsci_function(struct intel_display *display, u32 function) in check_swsci_function() argument
277 struct intel_opregion *opregion = display->opregion; in check_swsci_function()
307 static int swsci(struct intel_display *display, in swsci() argument
311 struct pci_dev *pdev = to_pci_dev(display->drm->dev); in swsci()
316 ret = check_swsci_function(display, function); in swsci()
320 swsci = display->opregion->swsci; in swsci()
338 drm_dbg(display->drm, "SWSCI request already in progress\n"); in swsci()
364 drm_dbg(display->drm, "SWSCI request timed out\n"); in swsci()
373 drm_dbg(display->drm, "SWSCI request error %u\n", scic); in swsci()
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H A Dintel_display.c152 skl_wa_827(struct intel_display *display, enum pipe pipe, bool enable) in skl_wa_827() argument
154 intel_de_rmw(display, CLKGATE_DIS_PSL(pipe), in skl_wa_827()
161 icl_wa_scalerclkgating(struct intel_display *display, enum pipe pipe, in icl_wa_scalerclkgating() argument
164 intel_de_rmw(display, CLKGATE_DIS_PSL(pipe), in icl_wa_scalerclkgating()
171 icl_wa_cursorclkgating(struct intel_display *display, enum pipe pipe, in icl_wa_cursorclkgating() argument
174 intel_de_rmw(display, CLKGATE_DIS_PSL(pipe), in icl_wa_cursorclkgating()
343 struct intel_display *display = to_intel_display(crtc_state); in intel_primary_crtc() local
346 return intel_crtc_for_pipe(display, joiner_primary_pipe(crtc_state)); in intel_primary_crtc()
354 struct intel_display *display = to_intel_display(old_crtc_state); in intel_wait_for_pipe_off() local
357 if (DISPLAY_VER(display) >= 4) { in intel_wait_for_pipe_off()
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H A Dintel_bios.c72 struct intel_display *display; member
151 bdb_find_section(struct intel_display *display, in bdb_find_section() argument
156 list_for_each_entry(entry, &display->vbt.bdb_blocks, node) { in bdb_find_section()
206 static size_t lfp_data_min_size(struct intel_display *display) in lfp_data_min_size() argument
211 ptrs = bdb_find_section(display, BDB_LFP_DATA_PTRS); in lfp_data_min_size()
366 static void *generate_lfp_data_ptrs(struct intel_display *display, in generate_lfp_data_ptrs() argument
380 if (display->vbt.version < 155) in generate_lfp_data_ptrs()
389 drm_dbg_kms(display->drm, "Generating LFP data table pointers\n"); in generate_lfp_data_ptrs()
457 init_bdb_block(struct intel_display *display, in init_bdb_block() argument
470 temp_block = generate_lfp_data_ptrs(display, bdb); in init_bdb_block()
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H A Dintel_pmdemand.c81 struct intel_display *display = to_intel_display(state); in intel_atomic_get_pmdemand_state() local
84 &display->pmdemand.obj); in intel_atomic_get_pmdemand_state()
95 struct intel_display *display = to_intel_display(state); in intel_atomic_get_old_pmdemand_state() local
98 &display->pmdemand.obj); in intel_atomic_get_old_pmdemand_state()
109 struct intel_display *display = to_intel_display(state); in intel_atomic_get_new_pmdemand_state() local
112 &display->pmdemand.obj); in intel_atomic_get_new_pmdemand_state()
120 int intel_pmdemand_init(struct intel_display *display) in intel_pmdemand_init() argument
128 intel_atomic_global_obj_init(display, &display->pmdemand.obj, in intel_pmdemand_init()
132 if (IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_C0)) in intel_pmdemand_init()
134 intel_de_rmw(display, XELPD_CHICKEN_DCPR_3, 0, DMD_RSP_TIMEOUT_DISABLE); in intel_pmdemand_init()
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H A Dintel_opregion.h37 int intel_opregion_setup(struct intel_display *display);
38 void intel_opregion_cleanup(struct intel_display *display);
40 void intel_opregion_register(struct intel_display *display);
41 void intel_opregion_unregister(struct intel_display *display);
43 void intel_opregion_resume(struct intel_display *display);
44 void intel_opregion_suspend(struct intel_display *display,
47 bool intel_opregion_asle_present(struct intel_display *display);
48 void intel_opregion_asle_intr(struct intel_display *display);
51 int intel_opregion_notify_adapter(struct intel_display *display,
53 int intel_opregion_get_panel_type(struct intel_display *display);
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H A Dintel_lvds.c87 bool intel_lvds_port_enabled(struct intel_display *display, in intel_lvds_port_enabled() argument
92 val = intel_de_read(display, lvds_reg); in intel_lvds_port_enabled()
95 if (HAS_PCH_CPT(display)) in intel_lvds_port_enabled()
106 struct intel_display *display = to_intel_display(encoder); in intel_lvds_get_hw_state() local
111 wakeref = intel_display_power_get_if_enabled(display, encoder->power_domain); in intel_lvds_get_hw_state()
115 ret = intel_lvds_port_enabled(display, lvds_encoder->reg, pipe); in intel_lvds_get_hw_state()
117 intel_display_power_put(display, encoder->power_domain, wakeref); in intel_lvds_get_hw_state()
125 struct intel_display *display = to_intel_display(encoder); in intel_lvds_get_config() local
131 tmp = intel_de_read(display, lvds_encoder->reg); in intel_lvds_get_config()
143 if (DISPLAY_VER(display) < 5) in intel_lvds_get_config()
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H A Dintel_frontbuffer.c83 static void frontbuffer_flush(struct intel_display *display, in frontbuffer_flush() argument
88 spin_lock(&display->fb_tracking.lock); in frontbuffer_flush()
89 frontbuffer_bits &= ~display->fb_tracking.busy_bits; in frontbuffer_flush()
90 spin_unlock(&display->fb_tracking.lock); in frontbuffer_flush()
95 trace_intel_frontbuffer_flush(display, frontbuffer_bits, origin); in frontbuffer_flush()
98 intel_td_flush(display); in frontbuffer_flush()
99 intel_drrs_flush(display, frontbuffer_bits); in frontbuffer_flush()
100 intel_psr_flush(display, frontbuffer_bits, origin); in frontbuffer_flush()
101 intel_fbc_flush(display, frontbuffer_bits, origin); in frontbuffer_flush()
115 void intel_frontbuffer_flip(struct intel_display *display, in intel_frontbuffer_flip() argument
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H A Dicl_dsi.c60 static int header_credits_available(struct intel_display *display, in header_credits_available() argument
63 return (intel_de_read(display, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK) in header_credits_available()
67 static int payload_credits_available(struct intel_display *display, in payload_credits_available() argument
70 return (intel_de_read(display, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK) in payload_credits_available()
74 static bool wait_for_header_credits(struct intel_display *display, in wait_for_header_credits() argument
79 ret = poll_timeout_us(available = header_credits_available(display, dsi_trans), in wait_for_header_credits()
83 drm_err(display->drm, "DSI header credits not released\n"); in wait_for_header_credits()
90 static bool wait_for_payload_credits(struct intel_display *display, in wait_for_payload_credits() argument
95 ret = poll_timeout_us(available = payload_credits_available(display, dsi_trans), in wait_for_payload_credits()
99 drm_err(display->drm, "DSI payload credits not released\n"); in wait_for_payload_credits()
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H A Dskl_watermark.c59 static void skl_sagv_disable(struct intel_display *display);
77 u8 intel_enabled_dbuf_slices_mask(struct intel_display *display) in intel_enabled_dbuf_slices_mask() argument
82 for_each_dbuf_slice(display, slice) { in intel_enabled_dbuf_slices_mask()
83 if (intel_de_read(display, DBUF_CTL_S(slice)) & DBUF_POWER_STATE) in intel_enabled_dbuf_slices_mask()
94 static bool skl_needs_memory_bw_wa(struct intel_display *display) in skl_needs_memory_bw_wa() argument
96 return DISPLAY_VER(display) == 9; in skl_needs_memory_bw_wa()
100 intel_has_sagv(struct intel_display *display) in intel_has_sagv() argument
102 return HAS_SAGV(display) && display->sagv.status != I915_SAGV_NOT_CONTROLLED; in intel_has_sagv()
106 intel_sagv_block_time(struct intel_display *display) in intel_sagv_block_time() argument
108 if (DISPLAY_VER(display) >= 14) { in intel_sagv_block_time()
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H A Dintel_hdcp_gsc_message.c23 struct intel_display *display; in intel_hdcp_gsc_initiate_session() local
29 display = to_intel_display(dev); in intel_hdcp_gsc_initiate_session()
30 if (!display) { in intel_hdcp_gsc_initiate_session()
34 gsc_context = display->hdcp.gsc_context; in intel_hdcp_gsc_initiate_session()
47 byte = intel_parent_hdcp_gsc_msg_send(display, gsc_context, in intel_hdcp_gsc_initiate_session()
51 drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); in intel_hdcp_gsc_initiate_session()
56 drm_dbg_kms(display->drm, "FW cmd 0x%08X Failed. Status: 0x%X\n", in intel_hdcp_gsc_initiate_session()
81 struct intel_display *display; in intel_hdcp_gsc_verify_receiver_cert_prepare_km() local
87 display = to_intel_display(dev); in intel_hdcp_gsc_verify_receiver_cert_prepare_km()
88 if (!display) { in intel_hdcp_gsc_verify_receiver_cert_prepare_km()
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H A Dg4x_dp.c56 const struct dpll *vlv_get_dpll(struct intel_display *display) in vlv_get_dpll() argument
58 return display->platform.cherryview ? &chv_dpll[0] : &vlv_dpll[0]; in vlv_get_dpll()
64 struct intel_display *display = to_intel_display(encoder); in g4x_dp_set_clock() local
68 if (display->platform.g4x) { in g4x_dp_set_clock()
71 } else if (HAS_PCH_SPLIT(display)) { in g4x_dp_set_clock()
74 } else if (display->platform.cherryview) { in g4x_dp_set_clock()
77 } else if (display->platform.valleyview) { in g4x_dp_set_clock()
96 struct intel_display *display = to_intel_display(encoder); in intel_dp_prepare() local
125 intel_dp->DP = intel_de_read(display, intel_dp->output_reg) & DP_DETECTED; in intel_dp_prepare()
133 if (display->platform.ivybridge && port == PORT_A) { in intel_dp_prepare()
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