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/linux/drivers/gpu/drm/i915/
H A DMakefile228 display/hsw_ips.o \
229 display/i9xx_display_sr.o \
230 display/i9xx_plane.o \
231 display/i9xx_wm.o \
232 display/intel_alpm.o \
233 display/intel_atomic.o \
234 display/intel_audio.o \
235 display/intel_bios.o \
236 display/intel_bo.o \
237 display/intel_bw.o \
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/linux/drivers/gpu/drm/xe/
H A DMakefile198 -I$(src)/display/ext \
200 -I$(srctree)/drivers/gpu/drm/i915/display/ \
209 $(obj)/i915-display/%.o: $(srctree)/drivers/gpu/drm/i915/display/%.c FORCE
215 display/ext/i915_irq.o \
216 display/intel_bo.o \
217 display/intel_fb_bo.o \
218 display/intel_fbdev_fb.o \
219 display/xe_display.o \
220 display/xe_display_misc.o \
221 display/xe_display_rpm.o \
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_audio.c191 static bool needs_wa_14020863754(struct intel_display *display) in needs_wa_14020863754() argument
193 return DISPLAY_VERx100(display) == 3000 || in needs_wa_14020863754()
194 DISPLAY_VERx100(display) == 2000 || in needs_wa_14020863754()
195 DISPLAY_VERx100(display) == 1401; in needs_wa_14020863754()
201 struct intel_display *display = to_intel_display(crtc_state); in audio_config_hdmi_pixel_clock() local
211 if (DISPLAY_VER(display) < 12 && adjusted_mode->crtc_clock > 148500) in audio_config_hdmi_pixel_clock()
215 drm_dbg_kms(display->drm, in audio_config_hdmi_pixel_clock()
221 drm_dbg_kms(display->drm, in audio_config_hdmi_pixel_clock()
256 static int g4x_eld_buffer_size(struct intel_display *display) in g4x_eld_buffer_size() argument
260 tmp = intel_de_read(display, G4X_AUD_CNTL_ST); in g4x_eld_buffer_size()
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H A Dvlv_dsi_regs.h14 #define _MIPI_MMIO_BASE(display) ((display)->dsi.mmio_base) argument
97 #define MIPI_DEVICE_READY(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DEVICE_R… argument
107 #define MIPI_INTR_STAT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_STAT,… argument
110 #define MIPI_INTR_EN(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_EN, _MI… argument
146 #define MIPI_DSI_FUNC_PRG(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DSI_FUNC… argument
169 #define MIPI_HS_TX_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_TX_T… argument
174 #define MIPI_LP_RX_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_RX_T… argument
179 #define MIPI_TURN_AROUND_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_T… argument
184 #define MIPI_DEVICE_RESET_TIMER(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DE… argument
189 #define MIPI_DPI_RESOLUTION(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPI_RE… argument
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H A Dintel_psr.c266 struct intel_display *display = to_intel_display(intel_dp); in panel_replay_global_enabled() local
269 display->params.enable_panel_replay; in panel_replay_global_enabled()
274 struct intel_display *display = to_intel_display(intel_dp); in psr_irq_psr_error_bit_get() local
276 return DISPLAY_VER(display) >= 12 ? TGL_PSR_ERROR : in psr_irq_psr_error_bit_get()
282 struct intel_display *display = to_intel_display(intel_dp); in psr_irq_post_exit_bit_get() local
284 return DISPLAY_VER(display) >= 12 ? TGL_PSR_POST_EXIT : in psr_irq_post_exit_bit_get()
290 struct intel_display *display = to_intel_display(intel_dp); in psr_irq_pre_entry_bit_get() local
292 return DISPLAY_VER(display) >= 12 ? TGL_PSR_PRE_ENTRY : in psr_irq_pre_entry_bit_get()
298 struct intel_display *display = to_intel_display(intel_dp); in psr_irq_mask_get() local
300 return DISPLAY_VER(display) >= 12 ? TGL_PSR_MASK : in psr_irq_mask_get()
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H A Dintel_display.c153 skl_wa_827(struct intel_display *display, enum pipe pipe, bool enable) in skl_wa_827() argument
155 intel_de_rmw(display, CLKGATE_DIS_PSL(pipe), in skl_wa_827()
162 icl_wa_scalerclkgating(struct intel_display *display, enum pipe pipe, in icl_wa_scalerclkgating() argument
165 intel_de_rmw(display, CLKGATE_DIS_PSL(pipe), in icl_wa_scalerclkgating()
172 icl_wa_cursorclkgating(struct intel_display *display, enum pipe pipe, in icl_wa_cursorclkgating() argument
175 intel_de_rmw(display, CLKGATE_DIS_PSL(pipe), in icl_wa_cursorclkgating()
344 struct intel_display *display = to_intel_display(crtc_state); in intel_primary_crtc() local
347 return intel_crtc_for_pipe(display, joiner_primary_pipe(crtc_state)); in intel_primary_crtc()
355 struct intel_display *display = to_intel_display(old_crtc_state); in intel_wait_for_pipe_off() local
358 if (DISPLAY_VER(display) >= 4) { in intel_wait_for_pipe_off()
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H A Dintel_opregion.h37 int intel_opregion_setup(struct intel_display *display);
38 void intel_opregion_cleanup(struct intel_display *display);
40 void intel_opregion_register(struct intel_display *display);
41 void intel_opregion_unregister(struct intel_display *display);
43 void intel_opregion_resume(struct intel_display *display);
44 void intel_opregion_suspend(struct intel_display *display,
47 bool intel_opregion_asle_present(struct intel_display *display);
48 void intel_opregion_asle_intr(struct intel_display *display);
51 int intel_opregion_notify_adapter(struct intel_display *display,
53 int intel_opregion_get_panel_type(struct intel_display *display);
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H A Dintel_frontbuffer.c83 static void frontbuffer_flush(struct intel_display *display, in frontbuffer_flush() argument
88 spin_lock(&display->fb_tracking.lock); in frontbuffer_flush()
89 frontbuffer_bits &= ~display->fb_tracking.busy_bits; in frontbuffer_flush()
90 spin_unlock(&display->fb_tracking.lock); in frontbuffer_flush()
95 trace_intel_frontbuffer_flush(display, frontbuffer_bits, origin); in frontbuffer_flush()
98 intel_td_flush(display); in frontbuffer_flush()
99 intel_drrs_flush(display, frontbuffer_bits); in frontbuffer_flush()
100 intel_psr_flush(display, frontbuffer_bits, origin); in frontbuffer_flush()
101 intel_fbc_flush(display, frontbuffer_bits, origin); in frontbuffer_flush()
115 void intel_frontbuffer_flip(struct intel_display *display, in intel_frontbuffer_flip() argument
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H A Dintel_color.c228 struct intel_display *display = to_intel_display(crtc->base.dev); in ilk_update_pipe_csc() local
231 intel_de_write_dsb(display, dsb, PIPE_CSC_PREOFF_HI(pipe), in ilk_update_pipe_csc()
233 intel_de_write_dsb(display, dsb, PIPE_CSC_PREOFF_ME(pipe), in ilk_update_pipe_csc()
235 intel_de_write_dsb(display, dsb, PIPE_CSC_PREOFF_LO(pipe), in ilk_update_pipe_csc()
238 intel_de_write_dsb(display, dsb, PIPE_CSC_COEFF_RY_GY(pipe), in ilk_update_pipe_csc()
240 intel_de_write_dsb(display, dsb, PIPE_CSC_COEFF_BY(pipe), in ilk_update_pipe_csc()
243 intel_de_write_dsb(display, dsb, PIPE_CSC_COEFF_RU_GU(pipe), in ilk_update_pipe_csc()
245 intel_de_write_dsb(display, dsb, PIPE_CSC_COEFF_BU(pipe), in ilk_update_pipe_csc()
248 intel_de_write_dsb(display, dsb, PIPE_CSC_COEFF_RV_GV(pipe), in ilk_update_pipe_csc()
250 intel_de_write_dsb(display, dsb, PIPE_CSC_COEFF_BV(pipe), in ilk_update_pipe_csc()
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H A Dintel_display_driver.h17 void intel_display_driver_init_hw(struct intel_display *display);
18 void intel_display_driver_early_probe(struct intel_display *display);
19 int intel_display_driver_probe_noirq(struct intel_display *display);
20 int intel_display_driver_probe_nogem(struct intel_display *display);
21 int intel_display_driver_probe(struct intel_display *display);
22 void intel_display_driver_register(struct intel_display *display);
23 void intel_display_driver_remove(struct intel_display *display);
24 void intel_display_driver_remove_noirq(struct intel_display *display);
25 void intel_display_driver_remove_nogem(struct intel_display *display);
26 void intel_display_driver_unregister(struct intel_display *display);
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H A Dskl_universal_plane.c241 static u8 icl_nv12_y_plane_mask(struct intel_display *display) in icl_nv12_y_plane_mask() argument
243 if (DISPLAY_VER(display) >= 13 || HAS_D12_PLANE_MINIMIZATION(display)) in icl_nv12_y_plane_mask()
249 bool icl_is_nv12_y_plane(struct intel_display *display, in icl_is_nv12_y_plane() argument
252 return DISPLAY_VER(display) >= 11 && in icl_is_nv12_y_plane()
253 icl_nv12_y_plane_mask(display) & BIT(plane_id); in icl_is_nv12_y_plane()
261 bool icl_is_hdr_plane(struct intel_display *display, enum plane_id plane_id) in icl_is_hdr_plane() argument
263 return DISPLAY_VER(display) >= 11 && in icl_is_hdr_plane()
449 static bool skl_plane_has_fbc(struct intel_display *display, in skl_plane_has_fbc() argument
452 if ((DISPLAY_RUNTIME_INFO(display)->fbc_mask & BIT(fbc_id)) == 0) in skl_plane_has_fbc()
455 if (DISPLAY_VER(display) >= 20) in skl_plane_has_fbc()
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H A Dintel_fbdev.c69 struct intel_display *display = to_intel_display(fb_helper->client.dev); in to_intel_fbdev() local
71 return display->fbdev.fbdev; in to_intel_fbdev()
226 __intel_fbdev_fb_alloc(struct intel_display *display, in __intel_fbdev_fb_alloc() argument
239 obj = intel_fbdev_fb_bo_create(display->drm, size); in __intel_fbdev_fb_alloc()
246 drm_get_format_info(display->drm, in __intel_fbdev_fb_alloc()
267 struct intel_display *display = to_intel_display(helper->dev); in intel_fbdev_driver_fbdev_probe() local
283 drm_dbg_kms(display->drm, in intel_fbdev_driver_fbdev_probe()
292 wakeref = intel_display_rpm_get(display); in intel_fbdev_driver_fbdev_probe()
294 if (!fb || drm_WARN_ON(display->drm, !intel_fb_bo(&fb->base))) { in intel_fbdev_driver_fbdev_probe()
295 drm_dbg_kms(display->drm, in intel_fbdev_driver_fbdev_probe()
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H A Dintel_fb.c26 #define check_array_bounds(display, a, i) drm_WARN_ON((display)->drm, (i) >= ARRAY_SIZE(a)) argument
546 static bool plane_has_modifier(struct intel_display *display, in plane_has_modifier() argument
550 if (!IS_DISPLAY_VER(display, md->display_ver.from, md->display_ver.until)) in plane_has_modifier()
561 HAS_AUX_CCS(display) != !!md->ccs.packed_aux_planes) in plane_has_modifier()
565 (DISPLAY_VER(display) < 14 || !display->platform.dgfx)) in plane_has_modifier()
569 (DISPLAY_VER(display) < 20 || display->platform.dgfx)) in plane_has_modifier()
584 u64 *intel_fb_plane_get_modifiers(struct intel_display *display, in intel_fb_plane_get_modifiers() argument
592 if (plane_has_modifier(display, plane_caps, &intel_modifiers[i])) in intel_fb_plane_get_modifiers()
597 if (drm_WARN_ON(display->drm, !list)) in intel_fb_plane_get_modifiers()
602 if (plane_has_modifier(display, plane_caps, &intel_modifiers[i])) in intel_fb_plane_get_modifiers()
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H A Dintel_acpi.h14 void intel_dsm_get_bios_data_funcs_supported(struct intel_display *display);
15 void intel_acpi_device_id_update(struct intel_display *display);
16 void intel_acpi_assign_connector_fwnodes(struct intel_display *display);
17 void intel_acpi_video_register(struct intel_display *display);
22 void intel_dsm_get_bios_data_funcs_supported(struct intel_display *display) { return; } in intel_dsm_get_bios_data_funcs_supported() argument
24 void intel_acpi_device_id_update(struct intel_display *display) { return; } in intel_acpi_device_id_update() argument
26 void intel_acpi_assign_connector_fwnodes(struct intel_display *display) { return; } in intel_acpi_assign_connector_fwnodes() argument
28 void intel_acpi_video_register(struct intel_display *display) { return; } in intel_acpi_video_register() argument
H A Dintel_display_reg_defs.h39 #define _MMIO_PIPE2(display, pipe, reg) _MMIO(DISPLAY_INFO(display)->pipe_offsets[(pipe)] - \ argument
40 DISPLAY_INFO(display)->pipe_offsets[PIPE_A] + \
41 DISPLAY_MMIO_BASE(display) + (reg))
42 #define _MMIO_TRANS2(display, tran, reg) _MMIO(DISPLAY_INFO(display)->trans_offsets[(tran)] - \ argument
43 DISPLAY_INFO(display)->trans_offsets[TRANSCODER_A] + \
44 DISPLAY_MMIO_BASE(display) + (reg))
45 #define _MMIO_CURSOR2(display, pipe, reg) _MMIO(DISPLAY_INFO(display)->cursor_offsets[(pipe)] - \ argument
46 DISPLAY_INFO(display)->cursor_offsets[PIPE_A] + \
47 DISPLAY_MMIO_BASE(display) + (reg))
H A Dintel_dmc_wl.h32 void intel_dmc_wl_init(struct intel_display *display);
33 void intel_dmc_wl_enable(struct intel_display *display, u32 dc_state);
34 void intel_dmc_wl_disable(struct intel_display *display);
35 void intel_dmc_wl_flush_release_work(struct intel_display *display);
36 void intel_dmc_wl_get(struct intel_display *display, i915_reg_t reg);
37 void intel_dmc_wl_put(struct intel_display *display, i915_reg_t reg);
38 void intel_dmc_wl_get_noreg(struct intel_display *display);
39 void intel_dmc_wl_put_noreg(struct intel_display *display);
H A Dintel_plane.c176 struct intel_display *display = to_intel_display(plane); in intel_plane_needs_physical() local
179 DISPLAY_INFO(display)->cursor_needs_physical; in intel_plane_needs_physical()
326 struct intel_display *display = to_intel_display(new_plane_state); in intel_plane_copy_uapi_plane_damage() local
330 if (DISPLAY_VER(display) < 12) in intel_plane_copy_uapi_plane_damage()
469 struct intel_display *display = to_intel_display(plane); in intel_plane_do_async_flip() local
490 return DISPLAY_VER(display) < 9 || old_crtc_state->uapi.async_flip; in intel_plane_do_async_flip()
594 struct intel_display *display = to_intel_display(new_crtc_state); in intel_plane_atomic_calc_changes() local
603 if (DISPLAY_VER(display) >= 9 && plane->id != PLANE_CURSOR) { in intel_plane_atomic_calc_changes()
612 if (!was_crtc_enabled && drm_WARN_ON(display->drm, was_visible)) in intel_plane_atomic_calc_changes()
636 drm_dbg_atomic(display->drm, in intel_plane_atomic_calc_changes()
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H A Dintel_dp_aux_backlight.c114 struct intel_display *display = to_intel_display(connector); in intel_dp_aux_supports_hdr_backlight() local
127 drm_dbg_kms(display->drm, in intel_dp_aux_supports_hdr_backlight()
147 if (display->params.enable_dpcd_backlight != INTEL_DP_AUX_BACKLIGHT_FORCE_INTEL && in intel_dp_aux_supports_hdr_backlight()
150 drm_info(display->drm, in intel_dp_aux_supports_hdr_backlight()
176 struct intel_display *display = to_intel_display(connector); in intel_dp_aux_hdr_get_backlight() local
183 drm_err(display->drm, in intel_dp_aux_hdr_get_backlight()
202 drm_err(display->drm, in intel_dp_aux_hdr_get_backlight()
248 struct intel_display *display = to_intel_display(connector); in intel_dp_aux_write_content_luminance() local
265 drm_dbg_kms(display->drm, in intel_dp_aux_write_content_luminance()
275 struct intel_display *display = to_intel_display(connector); in intel_dp_aux_fill_hdr_tcon_params() local
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H A Dintel_audio.h16 void intel_audio_hooks_init(struct intel_display *display);
28 void intel_audio_cdclk_change_pre(struct intel_display *display);
29 void intel_audio_cdclk_change_post(struct intel_display *display);
31 void intel_audio_init(struct intel_display *display);
32 void intel_audio_register(struct intel_display *display);
33 void intel_audio_deinit(struct intel_display *display);
/linux/drivers/acpi/acpica/
H A Dutbuffer.c34 void acpi_ut_dump_buffer(u8 *buffer, u32 count, u32 display, u32 base_offset) in acpi_ut_dump_buffer() argument
40 u32 display_data_only = display & DB_DISPLAY_DATA_ONLY; in acpi_ut_dump_buffer()
42 display &= ~DB_DISPLAY_DATA_ONLY; in acpi_ut_dump_buffer()
49 display = DB_BYTE_DISPLAY; in acpi_ut_dump_buffer()
69 acpi_os_printf("%*s", ((display * 2) + 1), " "); in acpi_ut_dump_buffer()
70 j += display; in acpi_ut_dump_buffer()
74 switch (display) { in acpi_ut_dump_buffer()
109 j += display; in acpi_ut_dump_buffer()
170 acpi_ut_debug_dump_buffer(u8 *buffer, u32 count, u32 display, u32 component_id) in acpi_ut_debug_dump_buffer() argument
180 acpi_ut_dump_buffer(buffer, count, display, 0); in acpi_ut_debug_dump_buffer()
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/linux/drivers/staging/fbtft/
H A Dfbtft-core.c496 struct fb_info *fbtft_framebuffer_alloc(struct fbtft_display *display, in fbtft_framebuffer_alloc() argument
508 int txbuflen = display->txbuflen; in fbtft_framebuffer_alloc()
509 unsigned int bpp = display->bpp; in fbtft_framebuffer_alloc()
510 unsigned int fps = display->fps; in fbtft_framebuffer_alloc()
512 const s16 *init_sequence = display->init_sequence; in fbtft_framebuffer_alloc()
513 char *gamma = display->gamma; in fbtft_framebuffer_alloc()
517 if (display->gamma_num * display->gamma_len > in fbtft_framebuffer_alloc()
540 if (pdata->display.init_sequence) in fbtft_framebuffer_alloc()
541 init_sequence = pdata->display.init_sequence; in fbtft_framebuffer_alloc()
544 if (pdata->display.debug) in fbtft_framebuffer_alloc()
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/linux/Documentation/devicetree/bindings/display/
H A Dcirrus,clps711x-fb.txt8 - display : phandle to a display node as described in
9 Documentation/devicetree/bindings/display/panel/display-timing.txt.
10 Additionally, the display node has to define properties:
25 display = <&display>;
28 display: display {
33 display-timings {
/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dnv50.c282 nv50_gr_mp_trap(struct nv50_gr *gr, int tpid, int display) in nv50_gr_mp_trap() argument
302 if (display) { in nv50_gr_mp_trap()
319 if (!mps && display) in nv50_gr_mp_trap()
326 u32 ustatus_new, int display, const char *name) in nv50_gr_tp_trap() argument
348 if (display) { in nv50_gr_tp_trap()
365 nv50_gr_mp_trap(gr, i, display); in nv50_gr_tp_trap()
368 if (ustatus && display) { in nv50_gr_tp_trap()
377 if (display) in nv50_gr_tp_trap()
384 if (display) in nv50_gr_tp_trap()
390 if (!tps && display) in nv50_gr_tp_trap()
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/linux/drivers/gpu/drm/msm/
H A DMakefile33 msm-display-$(CONFIG_DRM_MSM_HDMI) += \
47 msm-display-$(CONFIG_DRM_MSM_MDP4) += \
57 msm-display-$(CONFIG_DRM_MSM_MDP5) += \
70 msm-display-$(CONFIG_DRM_MSM_DPU) += \
101 msm-display-$(CONFIG_DRM_MSM_MDSS) += \
104 msm-display-$(CONFIG_DRM_MSM_KMS) += \
138 msm-display-$(CONFIG_DRM_MSM_DP)+= dp/dp_aux.o \
148 msm-display-$(CONFIG_DRM_MSM_HDMI_HDCP) += hdmi/hdmi_hdcp.o
150 msm-display-$(CONFIG_DRM_MSM_DSI) += dsi/dsi.o \
156 msm-display-$(CONFIG_DRM_MSM_DSI_28NM_PHY) += dsi/phy/dsi_phy_28nm.o
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/linux/Documentation/userspace-api/media/v4l/
H A Dext-ctrls-colorimetry.rst50 The mastering display defines the color volume (the color primaries,
51 white point and luminance range) of a display considered to be the
52 mastering display for the current video content.
66 primary component c of the mastering display in increments of 0.00002.
67 For describing the mastering display that uses Red, Green and Blue
74 primary component c of the mastering display in increments of 0.00002.
75 For describing the mastering display that uses Red, Green and Blue
82 point of the mastering display in increments of 0.00002.
86 point of the mastering display in increments of 0.00002.
89 - Specifies the nominal maximum display luminance of the mastering
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