55 	struct intel_display *display;  member
73 static struct intel_dmc *display_to_dmc(struct intel_display *display)  in display_to_dmc()  argument
75 	return display->dmc.dmc;  in display_to_dmc()
78 static const char *dmc_firmware_param(struct intel_display *display)  in dmc_firmware_param()  argument
80 	const char *p = display->params.dmc_firmware_path;  in dmc_firmware_param()
85 static bool dmc_firmware_param_disabled(struct intel_display *display)  in dmc_firmware_param_disabled()  argument
87 	const char *p = dmc_firmware_param(display);  in dmc_firmware_param_disabled()
168 static const char *dmc_firmware_default(struct intel_display *display, u32 *size)  in dmc_firmware_default()  argument
170 	struct drm_i915_private *i915 = to_i915(display->drm);  in dmc_firmware_default()
174 	if (DISPLAY_VERx100(display) == 3000) {  in dmc_firmware_default()
177 	} else if (DISPLAY_VERx100(display) == 2000) {  in dmc_firmware_default()
180 	} else if (DISPLAY_VERx100(display) == 1401) {  in dmc_firmware_default()
183 	} else if (DISPLAY_VERx100(display) == 1400) {  in dmc_firmware_default()
204 	} else if (DISPLAY_VER(display) == 11) {  in dmc_firmware_default()
385 static bool has_dmc_id_fw(struct intel_display *display, enum intel_dmc_id dmc_id)  in has_dmc_id_fw()  argument
387 	struct intel_dmc *dmc = display_to_dmc(display);  in has_dmc_id_fw()
392 bool intel_dmc_has_payload(struct intel_display *display)  in intel_dmc_has_payload()  argument
394 	return has_dmc_id_fw(display, DMC_FW_MAIN);  in intel_dmc_has_payload()
398 intel_get_stepping_info(struct intel_display *display,  in intel_get_stepping_info()  argument
401 	const char *step_name = intel_step_name(INTEL_DISPLAY_STEP(display));  in intel_get_stepping_info()
408 static void gen9_set_dc_state_debugmask(struct intel_display *display)  in gen9_set_dc_state_debugmask()  argument
411 	intel_de_rmw(display, DC_STATE_DEBUG, 0,  in gen9_set_dc_state_debugmask()
413 	intel_de_posting_read(display, DC_STATE_DEBUG);  in gen9_set_dc_state_debugmask()
416 static void disable_event_handler(struct intel_display *display,  in disable_event_handler()  argument
419 	intel_de_write(display, ctl_reg,  in disable_event_handler()
424 	intel_de_write(display, htp_reg, 0);  in disable_event_handler()
427 static void disable_all_event_handlers(struct intel_display *display)  in disable_all_event_handlers()  argument
432 	if (DISPLAY_VER(display) < 12)  in disable_all_event_handlers()
438 		if (!has_dmc_id_fw(display, dmc_id))  in disable_all_event_handlers()
442 			disable_event_handler(display,  in disable_all_event_handlers()
443 					      DMC_EVT_CTL(display, dmc_id, handler),  in disable_all_event_handlers()
444 					      DMC_EVT_HTP(display, dmc_id, handler));  in disable_all_event_handlers()
448 static void adlp_pipedmc_clock_gating_wa(struct intel_display *display, bool enable)  in adlp_pipedmc_clock_gating_wa()  argument
461 			intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe),  in adlp_pipedmc_clock_gating_wa()
465 			intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe),  in adlp_pipedmc_clock_gating_wa()
469 static void mtl_pipedmc_clock_gating_wa(struct intel_display *display)  in mtl_pipedmc_clock_gating_wa()  argument
476 	intel_de_rmw(display, GEN9_CLKGATE_DIS_0, 0,  in mtl_pipedmc_clock_gating_wa()
480 static void pipedmc_clock_gating_wa(struct intel_display *display, bool enable)  in pipedmc_clock_gating_wa()  argument
482 	if (DISPLAY_VER(display) >= 14 && enable)  in pipedmc_clock_gating_wa()
483 		mtl_pipedmc_clock_gating_wa(display);  in pipedmc_clock_gating_wa()
484 	else if (DISPLAY_VER(display) == 13)  in pipedmc_clock_gating_wa()
485 		adlp_pipedmc_clock_gating_wa(display, enable);  in pipedmc_clock_gating_wa()
488 void intel_dmc_enable_pipe(struct intel_display *display, enum pipe pipe)  in intel_dmc_enable_pipe()  argument
492 	if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id))  in intel_dmc_enable_pipe()
495 	if (DISPLAY_VER(display) >= 14)  in intel_dmc_enable_pipe()
496 		intel_de_rmw(display, MTL_PIPEDMC_CONTROL, 0, PIPEDMC_ENABLE_MTL(pipe));  in intel_dmc_enable_pipe()
498 		intel_de_rmw(display, PIPEDMC_CONTROL(pipe), 0, PIPEDMC_ENABLE);  in intel_dmc_enable_pipe()
501 void intel_dmc_disable_pipe(struct intel_display *display, enum pipe pipe)  in intel_dmc_disable_pipe()  argument
505 	if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id))  in intel_dmc_disable_pipe()
508 	if (DISPLAY_VER(display) >= 14)  in intel_dmc_disable_pipe()
509 		intel_de_rmw(display, MTL_PIPEDMC_CONTROL, PIPEDMC_ENABLE_MTL(pipe), 0);  in intel_dmc_disable_pipe()
511 		intel_de_rmw(display, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0);  in intel_dmc_disable_pipe()
514 static bool is_dmc_evt_ctl_reg(struct intel_display *display,  in is_dmc_evt_ctl_reg()  argument
518 	u32 start = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, 0));  in is_dmc_evt_ctl_reg()
519 	u32 end = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12));  in is_dmc_evt_ctl_reg()
524 static bool is_dmc_evt_htp_reg(struct intel_display *display,  in is_dmc_evt_htp_reg()  argument
528 	u32 start = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, 0));  in is_dmc_evt_htp_reg()
529 	u32 end = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12));  in is_dmc_evt_htp_reg()
534 static bool disable_dmc_evt(struct intel_display *display,  in disable_dmc_evt()  argument
538 	struct drm_i915_private *i915 = to_i915(display->drm);  in disable_dmc_evt()
540 	if (!is_dmc_evt_ctl_reg(display, dmc_id, reg))  in disable_dmc_evt()
560 static u32 dmc_mmiodata(struct intel_display *display,  in dmc_mmiodata()  argument
564 	if (disable_dmc_evt(display, dmc_id,  in dmc_mmiodata()
583 void intel_dmc_load_program(struct intel_display *display)  in intel_dmc_load_program()  argument
585 	struct drm_i915_private *i915 __maybe_unused = to_i915(display->drm);  in intel_dmc_load_program()
586 	struct i915_power_domains *power_domains = &display->power.domains;  in intel_dmc_load_program()
587 	struct intel_dmc *dmc = display_to_dmc(display);  in intel_dmc_load_program()
591 	if (!intel_dmc_has_payload(display))  in intel_dmc_load_program()
594 	pipedmc_clock_gating_wa(display, true);  in intel_dmc_load_program()
596 	disable_all_event_handlers(display);  in intel_dmc_load_program()
604 			intel_de_write_fw(display,  in intel_dmc_load_program()
614 			intel_de_write(display, dmc->dmc_info[dmc_id].mmioaddr[i],  in intel_dmc_load_program()
615 				       dmc_mmiodata(display, dmc, dmc_id, i));  in intel_dmc_load_program()
621 	gen9_set_dc_state_debugmask(display);  in intel_dmc_load_program()
623 	pipedmc_clock_gating_wa(display, false);  in intel_dmc_load_program()
633 void intel_dmc_disable_program(struct intel_display *display)  in intel_dmc_disable_program()  argument
635 	if (!intel_dmc_has_payload(display))  in intel_dmc_disable_program()
638 	pipedmc_clock_gating_wa(display, true);  in intel_dmc_disable_program()
639 	disable_all_event_handlers(display);  in intel_dmc_disable_program()
640 	pipedmc_clock_gating_wa(display, false);  in intel_dmc_disable_program()
642 	intel_dmc_wl_disable(display);  in intel_dmc_disable_program()
645 void assert_dmc_loaded(struct intel_display *display)  in assert_dmc_loaded()  argument
647 	struct intel_dmc *dmc = display_to_dmc(display);  in assert_dmc_loaded()
649 	drm_WARN_ONCE(display->drm, !dmc, "DMC not initialized\n");  in assert_dmc_loaded()
650 	drm_WARN_ONCE(display->drm, dmc &&  in assert_dmc_loaded()
651 		      !intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),  in assert_dmc_loaded()
653 	drm_WARN_ONCE(display->drm, !intel_de_read(display, DMC_SSP_BASE),  in assert_dmc_loaded()
655 	drm_WARN_ONCE(display->drm, !intel_de_read(display, DMC_HTP_SKL),  in assert_dmc_loaded()
686 	struct intel_display *display = dmc->display;  in dmc_set_fw_offset()  local
694 			drm_dbg(display->drm, "Unsupported firmware id: %u\n", dmc_id);  in dmc_set_fw_offset()
716 	struct intel_display *display = dmc->display;  in dmc_mmio_addr_sanity_check()  local
726 	} else if (DISPLAY_VER(display) >= 13) {  in dmc_mmio_addr_sanity_check()
729 	} else if (DISPLAY_VER(display) >= 12) {  in dmc_mmio_addr_sanity_check()
733 		drm_warn(display->drm, "Unknown mmio range for sanity check");  in dmc_mmio_addr_sanity_check()
749 	struct intel_display *display = dmc->display;  in parse_dmc_fw_header()  local
797 		drm_err(display->drm, "Unknown DMC fw header version: %u\n",  in parse_dmc_fw_header()
803 		drm_err(display->drm, "DMC firmware has wrong dmc header length "  in parse_dmc_fw_header()
810 		drm_err(display->drm, "DMC firmware has wrong mmio count %u\n", mmio_count);  in parse_dmc_fw_header()
816 		drm_err(display->drm, "DMC firmware has Wrong MMIO Addresses\n");  in parse_dmc_fw_header()
820 	drm_dbg_kms(display->drm, "DMC %d:\n", dmc_id);  in parse_dmc_fw_header()
825 		drm_dbg_kms(display->drm, " mmio[%d]: 0x%x = 0x%x%s%s\n",  in parse_dmc_fw_header()
827 			    is_dmc_evt_ctl_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_CTL)" :  in parse_dmc_fw_header()
828 			    is_dmc_evt_htp_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_HTP)" : "",  in parse_dmc_fw_header()
829 			    disable_dmc_evt(display, dmc_id, dmc_info->mmioaddr[i],  in parse_dmc_fw_header()
843 		drm_err(display->drm, "DMC FW too big (%u bytes)\n", payload_size);  in parse_dmc_fw_header()
858 	drm_err(display->drm, "Truncated DMC firmware, refusing.\n");  in parse_dmc_fw_header()
868 	struct intel_display *display = dmc->display;  in parse_dmc_fw_package()  local
881 		drm_err(display->drm, "DMC firmware has unknown header version %u\n",  in parse_dmc_fw_package()
895 		drm_err(display->drm, "DMC firmware has wrong package header length "  in parse_dmc_fw_package()
913 	drm_err(display->drm, "Truncated DMC firmware, refusing.\n");  in parse_dmc_fw_package()
922 	struct intel_display *display = dmc->display;  in parse_dmc_fw_css()  local
925 		drm_err(display->drm, "Truncated DMC firmware, refusing.\n");  in parse_dmc_fw_css()
931 		drm_err(display->drm, "DMC firmware has wrong CSS header length "  in parse_dmc_fw_css()
944 	struct intel_display *display = dmc->display;  in parse_dmc_fw()  local
949 	const struct stepping_info *si = intel_get_stepping_info(display, &display_info);  in parse_dmc_fw()
979 			drm_err(display->drm, "Reading beyond the fw_size\n");  in parse_dmc_fw()
987 	if (!intel_dmc_has_payload(display)) {  in parse_dmc_fw()
988 		drm_err(display->drm, "DMC firmware main program not found\n");  in parse_dmc_fw()
995 static void intel_dmc_runtime_pm_get(struct intel_display *display)  in intel_dmc_runtime_pm_get()  argument
997 	struct drm_i915_private *i915 = to_i915(display->drm);  in intel_dmc_runtime_pm_get()
999 	drm_WARN_ON(display->drm, display->dmc.wakeref);  in intel_dmc_runtime_pm_get()
1000 	display->dmc.wakeref = intel_display_power_get(i915, POWER_DOMAIN_INIT);  in intel_dmc_runtime_pm_get()
1003 static void intel_dmc_runtime_pm_put(struct intel_display *display)  in intel_dmc_runtime_pm_put()  argument
1005 	struct drm_i915_private *i915 = to_i915(display->drm);  in intel_dmc_runtime_pm_put()
1007 		fetch_and_zero(&display->dmc.wakeref);  in intel_dmc_runtime_pm_put()
1012 static const char *dmc_fallback_path(struct intel_display *display)  in dmc_fallback_path()  argument
1014 	struct drm_i915_private *i915 = to_i915(display->drm);  in dmc_fallback_path()
1025 	struct intel_display *display = dmc->display;  in dmc_load_work_fn()  local
1030 	err = request_firmware(&fw, dmc->fw_path, display->drm->dev);  in dmc_load_work_fn()
1032 	if (err == -ENOENT && !dmc_firmware_param(display)) {  in dmc_load_work_fn()
1033 		fallback_path = dmc_fallback_path(display);  in dmc_load_work_fn()
1035 			drm_dbg_kms(display->drm, "%s not found, falling back to %s\n",  in dmc_load_work_fn()
1037 			err = request_firmware(&fw, fallback_path, display->drm->dev);  in dmc_load_work_fn()
1044 		drm_notice(display->drm,  in dmc_load_work_fn()
1047 		drm_notice(display->drm, "DMC firmware homepage: %s",  in dmc_load_work_fn()
1054 		drm_notice(display->drm,  in dmc_load_work_fn()
1060 	intel_dmc_load_program(display);  in dmc_load_work_fn()
1061 	intel_dmc_runtime_pm_put(display);  in dmc_load_work_fn()
1063 	drm_info(display->drm, "Finished loading DMC firmware %s (v%u.%u)\n",  in dmc_load_work_fn()
1078 void intel_dmc_init(struct intel_display *display)  in intel_dmc_init()  argument
1080 	struct drm_i915_private *i915 = to_i915(display->drm);  in intel_dmc_init()
1083 	if (!HAS_DMC(display))  in intel_dmc_init()
1094 	intel_dmc_runtime_pm_get(display);  in intel_dmc_init()
1100 	dmc->display = display;  in intel_dmc_init()
1104 	dmc->fw_path = dmc_firmware_default(display, &dmc->max_fw_size);  in intel_dmc_init()
1106 	if (dmc_firmware_param_disabled(display)) {  in intel_dmc_init()
1107 		drm_info(display->drm, "Disabling DMC firmware and runtime PM\n");  in intel_dmc_init()
1111 	if (dmc_firmware_param(display))  in intel_dmc_init()
1112 		dmc->fw_path = dmc_firmware_param(display);  in intel_dmc_init()
1115 		drm_dbg_kms(display->drm,  in intel_dmc_init()
1120 	display->dmc.dmc = dmc;  in intel_dmc_init()
1122 	drm_dbg_kms(display->drm, "Loading %s\n", dmc->fw_path);  in intel_dmc_init()
1139 void intel_dmc_suspend(struct intel_display *display)  in intel_dmc_suspend()  argument
1141 	struct intel_dmc *dmc = display_to_dmc(display);  in intel_dmc_suspend()
1143 	if (!HAS_DMC(display))  in intel_dmc_suspend()
1149 	intel_dmc_wl_disable(display);  in intel_dmc_suspend()
1152 	if (!intel_dmc_has_payload(display))  in intel_dmc_suspend()
1153 		intel_dmc_runtime_pm_put(display);  in intel_dmc_suspend()
1163 void intel_dmc_resume(struct intel_display *display)  in intel_dmc_resume()  argument
1165 	if (!HAS_DMC(display))  in intel_dmc_resume()
1172 	if (!intel_dmc_has_payload(display))  in intel_dmc_resume()
1173 		intel_dmc_runtime_pm_get(display);  in intel_dmc_resume()
1183 void intel_dmc_fini(struct intel_display *display)  in intel_dmc_fini()  argument
1185 	struct intel_dmc *dmc = display_to_dmc(display);  in intel_dmc_fini()
1188 	if (!HAS_DMC(display))  in intel_dmc_fini()
1191 	intel_dmc_suspend(display);  in intel_dmc_fini()
1192 	drm_WARN_ON(display->drm, display->dmc.wakeref);  in intel_dmc_fini()
1199 		display->dmc.dmc = NULL;  in intel_dmc_fini()
1209 struct intel_dmc_snapshot *intel_dmc_snapshot_capture(struct intel_display *display)  in intel_dmc_snapshot_capture()  argument
1211 	struct intel_dmc *dmc = display_to_dmc(display);  in intel_dmc_snapshot_capture()
1214 	if (!HAS_DMC(display))  in intel_dmc_snapshot_capture()
1222 	snapshot->loaded = intel_dmc_has_payload(display);  in intel_dmc_snapshot_capture()
1244 	struct intel_display *display = m->private;  in intel_dmc_debugfs_status_show()  local
1245 	struct drm_i915_private *i915 = to_i915(display->drm);  in intel_dmc_debugfs_status_show()
1246 	struct intel_dmc *dmc = display_to_dmc(display);  in intel_dmc_debugfs_status_show()
1250 	if (!HAS_DMC(display))  in intel_dmc_debugfs_status_show()
1257 		   str_yes_no(intel_dmc_has_payload(display)));  in intel_dmc_debugfs_status_show()
1260 		   str_yes_no(DISPLAY_VER(display) >= 12));  in intel_dmc_debugfs_status_show()
1262 		   str_yes_no(has_dmc_id_fw(display, DMC_FW_PIPEA)));  in intel_dmc_debugfs_status_show()
1265 			      DISPLAY_VER(display) >= 14));  in intel_dmc_debugfs_status_show()
1267 		   str_yes_no(has_dmc_id_fw(display, DMC_FW_PIPEB)));  in intel_dmc_debugfs_status_show()
1269 	if (!intel_dmc_has_payload(display))  in intel_dmc_debugfs_status_show()
1275 	if (DISPLAY_VER(display) >= 12) {  in intel_dmc_debugfs_status_show()
1278 		if (IS_DGFX(i915) || DISPLAY_VER(display) >= 14) {  in intel_dmc_debugfs_status_show()
1288 			   intel_de_read(display, dc3co_reg));  in intel_dmc_debugfs_status_show()
1296 	seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(display, dc5_reg));  in intel_dmc_debugfs_status_show()
1299 			   intel_de_read(display, dc6_reg));  in intel_dmc_debugfs_status_show()
1302 		   intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));  in intel_dmc_debugfs_status_show()
1306 		   intel_de_read(display, DMC_SSP_BASE));  in intel_dmc_debugfs_status_show()
1307 	seq_printf(m, "htp: 0x%08x\n", intel_de_read(display, DMC_HTP_SKL));  in intel_dmc_debugfs_status_show()
1316 void intel_dmc_debugfs_register(struct intel_display *display)  in intel_dmc_debugfs_register()  argument
1318 	struct drm_minor *minor = display->drm->primary;  in intel_dmc_debugfs_register()
1321 			    display, &intel_dmc_debugfs_status_fops);  in intel_dmc_debugfs_register()