Lines Matching refs:display
55 * The display engine uses several different clocks to do its work. There
58 * are the core display clock (CDCLK) and RAWCLK.
60 * CDCLK clocks most of the display pipe logic, and thus its frequency
66 * to minimize power consumption for a given display configuration.
67 * Typically changes to the CDCLK frequency require all the display pipes
117 void (*get_cdclk)(struct intel_display *display,
119 void (*set_cdclk)(struct intel_display *display,
126 void intel_cdclk_get_cdclk(struct intel_display *display,
129 display->funcs.cdclk->get_cdclk(display, cdclk_config);
132 static void intel_cdclk_set_cdclk(struct intel_display *display,
136 display->funcs.cdclk->set_cdclk(display, cdclk_config, pipe);
141 struct intel_display *display = to_intel_display(state);
143 return display->funcs.cdclk->modeset_calc_cdclk(state);
146 static u8 intel_cdclk_calc_voltage_level(struct intel_display *display,
149 return display->funcs.cdclk->calc_voltage_level(cdclk);
152 static void fixed_133mhz_get_cdclk(struct intel_display *display,
158 static void fixed_200mhz_get_cdclk(struct intel_display *display,
164 static void fixed_266mhz_get_cdclk(struct intel_display *display,
170 static void fixed_333mhz_get_cdclk(struct intel_display *display,
176 static void fixed_400mhz_get_cdclk(struct intel_display *display,
182 static void fixed_450mhz_get_cdclk(struct intel_display *display,
188 static void i85x_get_cdclk(struct intel_display *display,
191 struct pci_dev *pdev = to_pci_dev(display->drm->dev);
230 static void i915gm_get_cdclk(struct intel_display *display,
233 struct pci_dev *pdev = to_pci_dev(display->drm->dev);
254 static void i945gm_get_cdclk(struct intel_display *display,
257 struct pci_dev *pdev = to_pci_dev(display->drm->dev);
278 static unsigned int intel_hpll_vco(struct intel_display *display)
322 if (display->platform.gm45)
324 else if (display->platform.g45)
326 else if (display->platform.i965gm)
328 else if (display->platform.pineview)
330 else if (display->platform.g33)
335 tmp = intel_de_read(display, display->platform.pineview ||
336 display->platform.mobile ? HPLLVCO_MOBILE : HPLLVCO);
340 drm_err(display->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n",
343 drm_dbg_kms(display->drm, "HPLL VCO %u kHz\n", vco);
348 static void g33_get_cdclk(struct intel_display *display,
351 struct pci_dev *pdev = to_pci_dev(display->drm->dev);
360 cdclk_config->vco = intel_hpll_vco(display);
391 drm_err(display->drm,
397 static void pnv_get_cdclk(struct intel_display *display,
400 struct pci_dev *pdev = to_pci_dev(display->drm->dev);
419 drm_err(display->drm,
420 "Unknown pnv display core clock 0x%04x\n", gcfgc);
431 static void i965gm_get_cdclk(struct intel_display *display,
434 struct pci_dev *pdev = to_pci_dev(display->drm->dev);
442 cdclk_config->vco = intel_hpll_vco(display);
470 drm_err(display->drm,
476 static void gm45_get_cdclk(struct intel_display *display,
479 struct pci_dev *pdev = to_pci_dev(display->drm->dev);
483 cdclk_config->vco = intel_hpll_vco(display);
499 drm_err(display->drm,
507 static void hsw_get_cdclk(struct intel_display *display,
510 u32 lcpll = intel_de_read(display, LCPLL_CTL);
515 else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT)
519 else if (display->platform.haswell_ult)
525 static int vlv_calc_cdclk(struct intel_display *display, int min_cdclk)
527 struct drm_i915_private *dev_priv = to_i915(display->drm);
536 if (display->platform.valleyview && min_cdclk > freq_320)
546 static u8 vlv_calc_voltage_level(struct intel_display *display, int cdclk)
548 struct drm_i915_private *dev_priv = to_i915(display->drm);
550 if (display->platform.valleyview) {
567 static void vlv_get_cdclk(struct intel_display *display,
570 struct drm_i915_private *dev_priv = to_i915(display->drm);
586 if (display->platform.valleyview)
594 static void vlv_program_pfi_credits(struct intel_display *display)
596 struct drm_i915_private *dev_priv = to_i915(display->drm);
599 if (display->platform.cherryview)
604 if (display->cdclk.hw.cdclk >= dev_priv->czclk_freq) {
606 if (display->platform.cherryview)
618 intel_de_write(display, GCI_CONTROL,
621 intel_de_write(display, GCI_CONTROL,
628 drm_WARN_ON(display->drm,
629 intel_de_read(display, GCI_CONTROL) & PFI_CREDIT_RESEND);
632 static void vlv_set_cdclk(struct intel_display *display,
636 struct drm_i915_private *dev_priv = to_i915(display->drm);
655 * issuing a modeset without actually changing any display after
656 * a system suspend. So grab the display core domain, which covers
659 wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE);
673 drm_err(display->drm,
692 drm_err(display->drm,
702 * so that the core display fetch happens in time to avoid underruns.
715 intel_update_cdclk(display);
717 vlv_program_pfi_credits(display);
719 intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);
722 static void chv_set_cdclk(struct intel_display *display,
726 struct drm_i915_private *dev_priv = to_i915(display->drm);
744 * issuing a modeset without actually changing any display after
745 * a system suspend. So grab the display core domain, which covers
748 wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE);
758 drm_err(display->drm,
764 intel_update_cdclk(display);
766 vlv_program_pfi_credits(display);
768 intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);
798 static void bdw_get_cdclk(struct intel_display *display,
801 u32 lcpll = intel_de_read(display, LCPLL_CTL);
806 else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT)
842 static void bdw_set_cdclk(struct intel_display *display,
846 struct drm_i915_private *dev_priv = to_i915(display->drm);
850 if (drm_WARN(display->drm,
851 (intel_de_read(display, LCPLL_CTL) &
861 drm_err(display->drm,
866 intel_de_rmw(display, LCPLL_CTL,
873 if (wait_for_us(intel_de_read(display, LCPLL_CTL) &
875 drm_err(display->drm, "Switching to FCLK failed\n");
877 intel_de_rmw(display, LCPLL_CTL,
880 intel_de_rmw(display, LCPLL_CTL,
883 if (wait_for_us((intel_de_read(display, LCPLL_CTL) &
885 drm_err(display->drm, "Switching back to LCPLL failed\n");
890 intel_de_write(display, CDCLK_FREQ,
893 intel_update_cdclk(display);
931 static void skl_dpll0_update(struct intel_display *display,
939 val = intel_de_read(display, LCPLL1_CTL);
943 if (drm_WARN_ON(display->drm, (val & LCPLL_PLL_LOCK) == 0))
946 val = intel_de_read(display, DPLL_CTRL1);
948 if (drm_WARN_ON(display->drm,
972 static void skl_get_cdclk(struct intel_display *display,
977 skl_dpll0_update(display, cdclk_config);
984 cdctl = intel_de_read(display, CDCLK_CTL);
1039 static void skl_set_preferred_cdclk_vco(struct intel_display *display, int vco)
1041 bool changed = display->cdclk.skl_preferred_vco_freq != vco;
1043 display->cdclk.skl_preferred_vco_freq = vco;
1046 intel_update_max_cdclk(display);
1049 static u32 skl_dpll0_link_rate(struct intel_display *display, int vco)
1051 drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000);
1068 static void skl_dpll0_enable(struct intel_display *display, int vco)
1070 intel_de_rmw(display, DPLL_CTRL1,
1075 skl_dpll0_link_rate(display, vco));
1076 intel_de_posting_read(display, DPLL_CTRL1);
1078 intel_de_rmw(display, LCPLL1_CTL,
1081 if (intel_de_wait_for_set(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 5))
1082 drm_err(display->drm, "DPLL0 not locked\n");
1084 display->cdclk.hw.vco = vco;
1087 skl_set_preferred_cdclk_vco(display, vco);
1090 static void skl_dpll0_disable(struct intel_display *display)
1092 intel_de_rmw(display, LCPLL1_CTL,
1095 if (intel_de_wait_for_clear(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 1))
1096 drm_err(display->drm, "Couldn't disable DPLL0\n");
1098 display->cdclk.hw.vco = 0;
1101 static u32 skl_cdclk_freq_sel(struct intel_display *display,
1106 drm_WARN_ON(display->drm,
1107 cdclk != display->cdclk.hw.bypass);
1108 drm_WARN_ON(display->drm, vco != 0);
1124 static void skl_set_cdclk(struct intel_display *display,
1128 struct drm_i915_private *dev_priv = to_i915(display->drm);
1142 drm_WARN_ON_ONCE(display->drm,
1143 display->platform.skylake && vco == 8640000);
1150 drm_err(display->drm,
1155 freq_select = skl_cdclk_freq_sel(display, cdclk, vco);
1157 if (display->cdclk.hw.vco != 0 &&
1158 display->cdclk.hw.vco != vco)
1159 skl_dpll0_disable(display);
1161 cdclk_ctl = intel_de_read(display, CDCLK_CTL);
1163 if (display->cdclk.hw.vco != vco) {
1167 intel_de_write(display, CDCLK_CTL, cdclk_ctl);
1172 intel_de_write(display, CDCLK_CTL, cdclk_ctl);
1173 intel_de_posting_read(display, CDCLK_CTL);
1175 if (display->cdclk.hw.vco != vco)
1176 skl_dpll0_enable(display, vco);
1180 intel_de_write(display, CDCLK_CTL, cdclk_ctl);
1183 intel_de_write(display, CDCLK_CTL, cdclk_ctl);
1187 intel_de_write(display, CDCLK_CTL, cdclk_ctl);
1188 intel_de_posting_read(display, CDCLK_CTL);
1194 intel_update_cdclk(display);
1197 static void skl_sanitize_cdclk(struct intel_display *display)
1202 * check if the pre-os initialized the display
1206 if ((intel_de_read(display, SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
1209 intel_update_cdclk(display);
1210 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK");
1213 if (display->cdclk.hw.vco == 0 ||
1214 display->cdclk.hw.cdclk == display->cdclk.hw.bypass)
1221 * enable display. Verify the same as well.
1223 cdctl = intel_de_read(display, CDCLK_CTL);
1225 skl_cdclk_decimal(display->cdclk.hw.cdclk);
1231 drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n");
1234 display->cdclk.hw.cdclk = 0;
1236 display->cdclk.hw.vco = ~0;
1239 static void skl_cdclk_init_hw(struct intel_display *display)
1243 skl_sanitize_cdclk(display);
1245 if (display->cdclk.hw.cdclk != 0 &&
1246 display->cdclk.hw.vco != 0) {
1251 if (display->cdclk.skl_preferred_vco_freq == 0)
1252 skl_set_preferred_cdclk_vco(display,
1253 display->cdclk.hw.vco);
1257 cdclk_config = display->cdclk.hw;
1259 cdclk_config.vco = display->cdclk.skl_preferred_vco_freq;
1265 skl_set_cdclk(display, &cdclk_config, INVALID_PIPE);
1268 static void skl_cdclk_uninit_hw(struct intel_display *display)
1270 struct intel_cdclk_config cdclk_config = display->cdclk.hw;
1276 skl_set_cdclk(display, &cdclk_config, INVALID_PIPE);
1517 static int bxt_calc_cdclk(struct intel_display *display, int min_cdclk)
1519 const struct intel_cdclk_vals *table = display->cdclk.table;
1523 if (table[i].refclk == display->cdclk.hw.ref &&
1527 drm_WARN(display->drm, 1,
1529 min_cdclk, display->cdclk.hw.ref);
1533 static int bxt_calc_cdclk_pll_vco(struct intel_display *display, int cdclk)
1535 const struct intel_cdclk_vals *table = display->cdclk.table;
1538 if (cdclk == display->cdclk.hw.bypass)
1542 if (table[i].refclk == display->cdclk.hw.ref &&
1544 return display->cdclk.hw.ref * table[i].ratio;
1546 drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n",
1547 cdclk, display->cdclk.hw.ref);
1639 static void icl_readout_refclk(struct intel_display *display,
1642 u32 dssm = intel_de_read(display, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK;
1660 static void bxt_de_pll_readout(struct intel_display *display,
1665 if (display->platform.dg2)
1667 else if (DISPLAY_VER(display) >= 11)
1668 icl_readout_refclk(display, cdclk_config);
1672 val = intel_de_read(display, BXT_DE_PLL_ENABLE);
1687 if (DISPLAY_VER(display) >= 11)
1690 ratio = intel_de_read(display, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
1695 static void bxt_get_cdclk(struct intel_display *display,
1702 bxt_de_pll_readout(display, cdclk_config);
1704 if (DISPLAY_VER(display) >= 12)
1706 else if (DISPLAY_VER(display) >= 11)
1716 divider = intel_de_read(display, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1736 if (HAS_CDCLK_SQUASH(display))
1737 squash_ctl = intel_de_read(display, CDCLK_SQUASH_CTL);
1753 if (DISPLAY_VER(display) >= 20)
1754 cdclk_config->joined_mbus = intel_de_read(display, MBUS_CTL) & MBUS_JOIN;
1760 intel_cdclk_calc_voltage_level(display, cdclk_config->cdclk);
1763 static void bxt_de_pll_disable(struct intel_display *display)
1765 intel_de_write(display, BXT_DE_PLL_ENABLE, 0);
1768 if (intel_de_wait_for_clear(display,
1770 drm_err(display->drm, "timeout waiting for DE PLL unlock\n");
1772 display->cdclk.hw.vco = 0;
1775 static void bxt_de_pll_enable(struct intel_display *display, int vco)
1777 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref);
1779 intel_de_rmw(display, BXT_DE_PLL_CTL,
1782 intel_de_write(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
1785 if (intel_de_wait_for_set(display,
1787 drm_err(display->drm, "timeout waiting for DE PLL lock\n");
1789 display->cdclk.hw.vco = vco;
1792 static void icl_cdclk_pll_disable(struct intel_display *display)
1794 intel_de_rmw(display, BXT_DE_PLL_ENABLE,
1798 if (intel_de_wait_for_clear(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
1799 drm_err(display->drm, "timeout waiting for CDCLK PLL unlock\n");
1801 display->cdclk.hw.vco = 0;
1804 static void icl_cdclk_pll_enable(struct intel_display *display, int vco)
1806 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref);
1810 intel_de_write(display, BXT_DE_PLL_ENABLE, val);
1813 intel_de_write(display, BXT_DE_PLL_ENABLE, val);
1816 if (intel_de_wait_for_set(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
1817 drm_err(display->drm, "timeout waiting for CDCLK PLL lock\n");
1819 display->cdclk.hw.vco = vco;
1822 static void adlp_cdclk_pll_crawl(struct intel_display *display, int vco)
1824 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref);
1829 intel_de_write(display, BXT_DE_PLL_ENABLE, val);
1833 intel_de_write(display, BXT_DE_PLL_ENABLE, val);
1836 if (intel_de_wait_for_set(display, BXT_DE_PLL_ENABLE,
1838 drm_err(display->drm, "timeout waiting for FREQ change request ack\n");
1841 intel_de_write(display, BXT_DE_PLL_ENABLE, val);
1843 display->cdclk.hw.vco = vco;
1846 static u32 bxt_cdclk_cd2x_pipe(struct intel_display *display, enum pipe pipe)
1848 if (DISPLAY_VER(display) >= 12) {
1853 } else if (DISPLAY_VER(display) >= 11) {
1866 static u32 bxt_cdclk_cd2x_div_sel(struct intel_display *display,
1872 drm_WARN_ON(display->drm,
1873 cdclk != display->cdclk.hw.bypass);
1874 drm_WARN_ON(display->drm, vco != 0);
1887 static u16 cdclk_squash_waveform(struct intel_display *display,
1890 const struct intel_cdclk_vals *table = display->cdclk.table;
1893 if (cdclk == display->cdclk.hw.bypass)
1897 if (table[i].refclk == display->cdclk.hw.ref &&
1901 drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n",
1902 cdclk, display->cdclk.hw.ref);
1907 static void icl_cdclk_pll_update(struct intel_display *display, int vco)
1909 if (display->cdclk.hw.vco != 0 &&
1910 display->cdclk.hw.vco != vco)
1911 icl_cdclk_pll_disable(display);
1913 if (display->cdclk.hw.vco != vco)
1914 icl_cdclk_pll_enable(display, vco);
1917 static void bxt_cdclk_pll_update(struct intel_display *display, int vco)
1919 if (display->cdclk.hw.vco != 0 &&
1920 display->cdclk.hw.vco != vco)
1921 bxt_de_pll_disable(display);
1923 if (display->cdclk.hw.vco != vco)
1924 bxt_de_pll_enable(display, vco);
1927 static void dg2_cdclk_squash_program(struct intel_display *display,
1936 intel_de_write(display, CDCLK_SQUASH_CTL, squash_ctl);
1949 static bool mdclk_source_is_cdclk_pll(struct intel_display *display)
1951 return DISPLAY_VER(display) >= 20;
1954 static u32 xe2lpd_mdclk_source_sel(struct intel_display *display)
1956 if (mdclk_source_is_cdclk_pll(display))
1962 int intel_mdclk_cdclk_ratio(struct intel_display *display,
1965 if (mdclk_source_is_cdclk_pll(display))
1972 static void xe2lpd_mdclk_cdclk_ratio_program(struct intel_display *display,
1975 intel_dbuf_mdclk_cdclk_ratio_update(display,
1976 intel_mdclk_cdclk_ratio(display, cdclk_config),
1980 static bool cdclk_compute_crawl_and_squash_midpoint(struct intel_display *display,
1993 if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display))
1996 old_waveform = cdclk_squash_waveform(display, old_cdclk_config->cdclk);
1997 new_waveform = cdclk_squash_waveform(display, new_cdclk_config->cdclk);
2014 if (drm_WARN_ON(display->drm, old_div != new_div))
2043 drm_WARN_ON(display->drm, mid_cdclk_config->cdclk <
2045 drm_WARN_ON(display->drm, mid_cdclk_config->cdclk >
2046 display->cdclk.max_cdclk_freq);
2047 drm_WARN_ON(display->drm, cdclk_squash_waveform(display, mid_cdclk_config->cdclk) !=
2053 static bool pll_enable_wa_needed(struct intel_display *display)
2055 return (DISPLAY_VERx100(display) == 2000 ||
2056 DISPLAY_VERx100(display) == 1400 ||
2057 display->platform.dg2) &&
2058 display->cdclk.hw.vco > 0;
2061 static u32 bxt_cdclk_ctl(struct intel_display *display,
2070 waveform = cdclk_squash_waveform(display, cdclk);
2072 val = bxt_cdclk_cd2x_div_sel(display, cdclk, vco, waveform) |
2073 bxt_cdclk_cd2x_pipe(display, pipe);
2079 if ((display->platform.geminilake || display->platform.broxton) &&
2083 if (DISPLAY_VER(display) >= 20)
2084 val |= xe2lpd_mdclk_source_sel(display);
2091 static void _bxt_set_cdclk(struct intel_display *display,
2098 if (HAS_CDCLK_CRAWL(display) && display->cdclk.hw.vco > 0 && vco > 0 &&
2099 !cdclk_pll_is_unknown(display->cdclk.hw.vco)) {
2100 if (display->cdclk.hw.vco != vco)
2101 adlp_cdclk_pll_crawl(display, vco);
2102 } else if (DISPLAY_VER(display) >= 11) {
2104 if (pll_enable_wa_needed(display))
2105 dg2_cdclk_squash_program(display, 0);
2107 icl_cdclk_pll_update(display, vco);
2109 bxt_cdclk_pll_update(display, vco);
2112 if (HAS_CDCLK_SQUASH(display)) {
2113 u16 waveform = cdclk_squash_waveform(display, cdclk);
2115 dg2_cdclk_squash_program(display, waveform);
2118 intel_de_write(display, CDCLK_CTL, bxt_cdclk_ctl(display, cdclk_config, pipe));
2121 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, pipe));
2124 static void bxt_set_cdclk(struct intel_display *display,
2128 struct drm_i915_private *dev_priv = to_i915(display->drm);
2139 if (DISPLAY_VER(display) >= 14 || display->platform.dg2)
2141 else if (DISPLAY_VER(display) >= 11)
2156 drm_err(display->drm,
2162 if (DISPLAY_VER(display) >= 20 && cdclk < display->cdclk.hw.cdclk)
2163 xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config);
2165 if (cdclk_compute_crawl_and_squash_midpoint(display, &display->cdclk.hw,
2167 _bxt_set_cdclk(display, &mid_cdclk_config, pipe);
2168 _bxt_set_cdclk(display, cdclk_config, pipe);
2170 _bxt_set_cdclk(display, cdclk_config, pipe);
2173 if (DISPLAY_VER(display) >= 20 && cdclk > display->cdclk.hw.cdclk)
2174 xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config);
2176 if (DISPLAY_VER(display) >= 14)
2181 else if (DISPLAY_VER(display) >= 11 && !display->platform.dg2)
2184 if (DISPLAY_VER(display) < 11) {
2197 drm_err(display->drm,
2203 intel_update_cdclk(display);
2205 if (DISPLAY_VER(display) >= 11)
2210 display->cdclk.hw.voltage_level = cdclk_config->voltage_level;
2213 static void bxt_sanitize_cdclk(struct intel_display *display)
2218 intel_update_cdclk(display);
2219 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK");
2221 if (display->cdclk.hw.vco == 0 ||
2222 display->cdclk.hw.cdclk == display->cdclk.hw.bypass)
2226 cdclk = bxt_calc_cdclk(display, display->cdclk.hw.cdclk);
2227 if (cdclk != display->cdclk.hw.cdclk)
2231 vco = bxt_calc_cdclk_pll_vco(display, cdclk);
2232 if (vco != display->cdclk.hw.vco)
2240 cdctl = intel_de_read(display, CDCLK_CTL);
2241 expected = bxt_cdclk_ctl(display, &display->cdclk.hw, INVALID_PIPE);
2248 cdctl &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE);
2249 expected &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE);
2256 drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n");
2259 display->cdclk.hw.cdclk = 0;
2262 display->cdclk.hw.vco = ~0;
2265 static void bxt_cdclk_init_hw(struct intel_display *display)
2269 bxt_sanitize_cdclk(display);
2271 if (display->cdclk.hw.cdclk != 0 &&
2272 display->cdclk.hw.vco != 0)
2275 cdclk_config = display->cdclk.hw;
2282 cdclk_config.cdclk = bxt_calc_cdclk(display, 0);
2283 cdclk_config.vco = bxt_calc_cdclk_pll_vco(display, cdclk_config.cdclk);
2285 intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk);
2287 bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE);
2290 static void bxt_cdclk_uninit_hw(struct intel_display *display)
2292 struct intel_cdclk_config cdclk_config = display->cdclk.hw;
2297 intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk);
2299 bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE);
2304 * @display: display instance
2306 * Initialize CDCLK. This consists mainly of initializing display->cdclk.hw and
2308 * during the display core initialization sequence, after which the DMC will
2311 void intel_cdclk_init_hw(struct intel_display *display)
2313 if (DISPLAY_VER(display) >= 10 || display->platform.broxton)
2314 bxt_cdclk_init_hw(display);
2315 else if (DISPLAY_VER(display) == 9)
2316 skl_cdclk_init_hw(display);
2321 * @display: display instance
2323 * Uninitialize CDCLK. This is done only during the display core
2326 void intel_cdclk_uninit_hw(struct intel_display *display)
2328 if (DISPLAY_VER(display) >= 10 || display->platform.broxton)
2329 bxt_cdclk_uninit_hw(display);
2330 else if (DISPLAY_VER(display) == 9)
2331 skl_cdclk_uninit_hw(display);
2334 static bool intel_cdclk_can_crawl_and_squash(struct intel_display *display,
2341 drm_WARN_ON(display->drm, cdclk_pll_is_unknown(a->vco));
2346 if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display))
2349 old_waveform = cdclk_squash_waveform(display, a->cdclk);
2350 new_waveform = cdclk_squash_waveform(display, b->cdclk);
2356 static bool intel_cdclk_can_crawl(struct intel_display *display,
2362 if (!HAS_CDCLK_CRAWL(display))
2378 static bool intel_cdclk_can_squash(struct intel_display *display,
2388 if (!HAS_CDCLK_SQUASH(display))
2417 * @display: display instance
2425 static bool intel_cdclk_can_cd2x_update(struct intel_display *display,
2430 if (DISPLAY_VER(display) < 10 && !display->platform.broxton)
2439 if (HAS_CDCLK_SQUASH(display))
2463 void intel_cdclk_dump_config(struct intel_display *display,
2467 drm_dbg_kms(display->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n",
2473 static void intel_pcode_notify(struct intel_display *display,
2480 struct drm_i915_private *i915 = to_i915(display->drm);
2484 if (!display->platform.dg2)
2501 drm_err(display->drm,
2502 "Failed to inform PCU about display config (err %d)\n",
2506 static void intel_set_cdclk(struct intel_display *display,
2512 if (!intel_cdclk_changed(&display->cdclk.hw, cdclk_config))
2515 if (drm_WARN_ON_ONCE(display->drm, !display->funcs.cdclk->set_cdclk))
2518 intel_cdclk_dump_config(display, cdclk_config, context);
2520 for_each_intel_encoder_with_psr(display->drm, encoder) {
2526 intel_audio_cdclk_change_pre(display);
2533 mutex_lock(&display->gmbus.mutex);
2534 for_each_intel_dp(display->drm, encoder) {
2538 &display->gmbus.mutex);
2541 intel_cdclk_set_cdclk(display, cdclk_config, pipe);
2543 for_each_intel_dp(display->drm, encoder) {
2548 mutex_unlock(&display->gmbus.mutex);
2550 for_each_intel_encoder_with_psr(display->drm, encoder) {
2556 intel_audio_cdclk_change_post(display);
2558 if (drm_WARN(display->drm,
2559 intel_cdclk_changed(&display->cdclk.hw, cdclk_config),
2561 intel_cdclk_dump_config(display, &display->cdclk.hw, "[hw state]");
2562 intel_cdclk_dump_config(display, cdclk_config, "[sw state]");
2568 struct intel_display *display = to_intel_display(state);
2607 intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk,
2613 struct intel_display *display = to_intel_display(state);
2644 intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk,
2669 struct intel_display *display = to_intel_display(state);
2681 if (display->platform.dg2)
2706 drm_WARN_ON(display->drm, !new_cdclk_state->base.changed);
2708 intel_set_cdclk(display, &cdclk_config, pipe,
2722 struct intel_display *display = to_intel_display(state);
2733 if (display->platform.dg2)
2742 drm_WARN_ON(display->drm, !new_cdclk_state->base.changed);
2744 intel_set_cdclk(display, &new_cdclk_state->actual, pipe,
2749 static int intel_cdclk_ppc(struct intel_display *display, bool double_wide)
2751 return DISPLAY_VER(display) >= 10 || double_wide ? 2 : 1;
2755 static int intel_cdclk_guardband(struct intel_display *display)
2757 if (DISPLAY_VER(display) >= 9 ||
2758 display->platform.broadwell || display->platform.haswell)
2760 else if (display->platform.cherryview)
2768 struct intel_display *display = to_intel_display(crtc_state);
2769 int ppc = intel_cdclk_ppc(display, crtc_state->double_wide);
2770 int guardband = intel_cdclk_guardband(display);
2779 struct intel_display *display = to_intel_display(crtc);
2783 for_each_intel_plane_on_crtc(display->drm, crtc, plane)
2808 struct intel_display *display = to_intel_display(state);
2836 min_cdclk = intel_bw_min_cdclk(display, bw_state);
2851 for_each_pipe(display, pipe)
2862 if (display->platform.geminilake && cdclk_state->active_pipes &&
2866 if (min_cdclk > display->cdclk.max_cdclk_freq) {
2867 drm_dbg_kms(display->drm,
2869 min_cdclk, display->cdclk.max_cdclk_freq);
2891 struct intel_display *display = to_intel_display(state);
2919 for_each_pipe(display, pipe)
2928 struct intel_display *display = to_intel_display(state);
2937 cdclk = vlv_calc_cdclk(display, min_cdclk);
2941 vlv_calc_voltage_level(display, cdclk);
2944 cdclk = vlv_calc_cdclk(display, cdclk_state->force_min_cdclk);
2948 vlv_calc_voltage_level(display, cdclk);
2987 struct intel_display *display = to_intel_display(state);
2996 vco = display->cdclk.skl_preferred_vco_freq;
3058 struct intel_display *display = to_intel_display(state);
3071 cdclk = bxt_calc_cdclk(display, min_cdclk);
3072 vco = bxt_calc_cdclk_pll_vco(display, cdclk);
3078 intel_cdclk_calc_voltage_level(display, cdclk));
3081 cdclk = bxt_calc_cdclk(display, cdclk_state->force_min_cdclk);
3082 vco = bxt_calc_cdclk_pll_vco(display, cdclk);
3087 intel_cdclk_calc_voltage_level(display, cdclk);
3139 struct intel_display *display = to_intel_display(state);
3142 cdclk_state = intel_atomic_get_global_obj_state(state, &display->cdclk.obj);
3198 int intel_cdclk_init(struct intel_display *display)
3206 intel_atomic_global_obj_init(display, &display->cdclk.obj,
3212 static bool intel_cdclk_need_serialize(struct intel_display *display,
3224 return cdclk_changed || (display->platform.dg2 && power_well_cnt_changed);
3229 struct intel_display *display = to_intel_display(state);
3248 if (intel_cdclk_need_serialize(display, old_cdclk_state, new_cdclk_state)) {
3268 intel_cdclk_can_cd2x_update(display,
3275 crtc = intel_crtc_for_pipe(display, pipe);
3285 if (intel_cdclk_can_crawl_and_squash(display,
3288 drm_dbg_kms(display->drm,
3290 } else if (intel_cdclk_can_squash(display,
3293 drm_dbg_kms(display->drm,
3295 } else if (intel_cdclk_can_crawl(display,
3298 drm_dbg_kms(display->drm,
3303 drm_dbg_kms(display->drm,
3315 drm_dbg_kms(display->drm,
3319 if (intel_mdclk_cdclk_ratio(display, &old_cdclk_state->actual) !=
3320 intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual)) {
3321 int ratio = intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual);
3328 drm_dbg_kms(display->drm,
3332 drm_dbg_kms(display->drm,
3340 void intel_cdclk_update_hw_state(struct intel_display *display)
3343 to_intel_bw_state(display->bw.obj.state);
3345 to_intel_cdclk_state(display->cdclk.obj.state);
3350 for_each_intel_crtc(display->drm, crtc) {
3362 cdclk_state->bw_min_cdclk = intel_bw_min_cdclk(display, bw_state);
3367 struct intel_display *display = to_intel_display(crtc);
3369 intel_cdclk_update_hw_state(display);
3372 static int intel_compute_max_dotclk(struct intel_display *display)
3374 int ppc = intel_cdclk_ppc(display, HAS_DOUBLE_WIDE(display));
3375 int guardband = intel_cdclk_guardband(display);
3376 int max_cdclk_freq = display->cdclk.max_cdclk_freq;
3383 * @display: display instance
3389 void intel_update_max_cdclk(struct intel_display *display)
3391 if (DISPLAY_VER(display) >= 30) {
3392 display->cdclk.max_cdclk_freq = 691200;
3393 } else if (display->platform.jasperlake || display->platform.elkhartlake) {
3394 if (display->cdclk.hw.ref == 24000)
3395 display->cdclk.max_cdclk_freq = 552000;
3397 display->cdclk.max_cdclk_freq = 556800;
3398 } else if (DISPLAY_VER(display) >= 11) {
3399 if (display->cdclk.hw.ref == 24000)
3400 display->cdclk.max_cdclk_freq = 648000;
3402 display->cdclk.max_cdclk_freq = 652800;
3403 } else if (display->platform.geminilake) {
3404 display->cdclk.max_cdclk_freq = 316800;
3405 } else if (display->platform.broxton) {
3406 display->cdclk.max_cdclk_freq = 624000;
3407 } else if (DISPLAY_VER(display) == 9) {
3408 u32 limit = intel_de_read(display, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
3411 vco = display->cdclk.skl_preferred_vco_freq;
3412 drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000);
3428 display->cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
3429 } else if (display->platform.broadwell) {
3436 if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT)
3437 display->cdclk.max_cdclk_freq = 450000;
3438 else if (display->platform.broadwell_ulx)
3439 display->cdclk.max_cdclk_freq = 450000;
3440 else if (display->platform.broadwell_ult)
3441 display->cdclk.max_cdclk_freq = 540000;
3443 display->cdclk.max_cdclk_freq = 675000;
3444 } else if (display->platform.cherryview) {
3445 display->cdclk.max_cdclk_freq = 320000;
3446 } else if (display->platform.valleyview) {
3447 display->cdclk.max_cdclk_freq = 400000;
3450 display->cdclk.max_cdclk_freq = display->cdclk.hw.cdclk;
3453 display->cdclk.max_dotclk_freq = intel_compute_max_dotclk(display);
3455 drm_dbg(display->drm, "Max CD clock rate: %d kHz\n",
3456 display->cdclk.max_cdclk_freq);
3458 drm_dbg(display->drm, "Max dotclock rate: %d kHz\n",
3459 display->cdclk.max_dotclk_freq);
3464 * @display: display instance
3468 void intel_update_cdclk(struct intel_display *display)
3470 intel_cdclk_get_cdclk(display, &display->cdclk.hw);
3478 if (display->platform.valleyview || display->platform.cherryview)
3479 intel_de_write(display, GMBUSFREQ_VLV,
3480 DIV_ROUND_UP(display->cdclk.hw.cdclk, 1000));
3483 static int dg1_rawclk(struct intel_display *display)
3489 intel_de_write(display, PCH_RAWCLK_FREQ,
3495 static int cnp_rawclk(struct intel_display *display)
3500 if (intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
3516 if (INTEL_PCH_TYPE(display) >= PCH_ICP)
3520 intel_de_write(display, PCH_RAWCLK_FREQ, rawclk);
3524 static int pch_rawclk(struct intel_display *display)
3526 return (intel_de_read(display, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
3529 static int vlv_hrawclk(struct intel_display *display)
3531 struct drm_i915_private *dev_priv = to_i915(display->drm);
3538 static int i9xx_hrawclk(struct intel_display *display)
3540 struct drm_i915_private *i915 = to_i915(display->drm);
3548 * @display: display instance
3553 u32 intel_read_rawclk(struct intel_display *display)
3557 if (INTEL_PCH_TYPE(display) >= PCH_MTL)
3564 else if (INTEL_PCH_TYPE(display) >= PCH_DG1)
3565 freq = dg1_rawclk(display);
3566 else if (INTEL_PCH_TYPE(display) >= PCH_CNP)
3567 freq = cnp_rawclk(display);
3568 else if (HAS_PCH_SPLIT(display))
3569 freq = pch_rawclk(display);
3570 else if (display->platform.valleyview || display->platform.cherryview)
3571 freq = vlv_hrawclk(display);
3572 else if (DISPLAY_VER(display) >= 3)
3573 freq = i9xx_hrawclk(display);
3583 struct intel_display *display = m->private;
3585 seq_printf(m, "Current CD clock frequency: %d kHz\n", display->cdclk.hw.cdclk);
3586 seq_printf(m, "Max CD clock frequency: %d kHz\n", display->cdclk.max_cdclk_freq);
3587 seq_printf(m, "Max pixel clock frequency: %d kHz\n", display->cdclk.max_dotclk_freq);
3594 void intel_cdclk_debugfs_register(struct intel_display *display)
3596 struct drm_minor *minor = display->drm->primary;
3599 display, &i915_cdclk_info_fops);
3747 * @display: display instance
3749 void intel_init_cdclk_hooks(struct intel_display *display)
3751 if (DISPLAY_VER(display) >= 30) {
3752 display->funcs.cdclk = &xe3lpd_cdclk_funcs;
3753 display->cdclk.table = xe3lpd_cdclk_table;
3754 } else if (DISPLAY_VER(display) >= 20) {
3755 display->funcs.cdclk = &rplu_cdclk_funcs;
3756 display->cdclk.table = xe2lpd_cdclk_table;
3757 } else if (DISPLAY_VERx100(display) >= 1401) {
3758 display->funcs.cdclk = &rplu_cdclk_funcs;
3759 display->cdclk.table = xe2hpd_cdclk_table;
3760 } else if (DISPLAY_VER(display) >= 14) {
3761 display->funcs.cdclk = &rplu_cdclk_funcs;
3762 display->cdclk.table = mtl_cdclk_table;
3763 } else if (display->platform.dg2) {
3764 display->funcs.cdclk = &tgl_cdclk_funcs;
3765 display->cdclk.table = dg2_cdclk_table;
3766 } else if (display->platform.alderlake_p) {
3768 if (display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) {
3769 display->cdclk.table = adlp_a_step_cdclk_table;
3770 display->funcs.cdclk = &tgl_cdclk_funcs;
3771 } else if (display->platform.alderlake_p_raptorlake_u) {
3772 display->cdclk.table = rplu_cdclk_table;
3773 display->funcs.cdclk = &rplu_cdclk_funcs;
3775 display->cdclk.table = adlp_cdclk_table;
3776 display->funcs.cdclk = &tgl_cdclk_funcs;
3778 } else if (display->platform.rocketlake) {
3779 display->funcs.cdclk = &tgl_cdclk_funcs;
3780 display->cdclk.table = rkl_cdclk_table;
3781 } else if (DISPLAY_VER(display) >= 12) {
3782 display->funcs.cdclk = &tgl_cdclk_funcs;
3783 display->cdclk.table = icl_cdclk_table;
3784 } else if (display->platform.jasperlake || display->platform.elkhartlake) {
3785 display->funcs.cdclk = &ehl_cdclk_funcs;
3786 display->cdclk.table = icl_cdclk_table;
3787 } else if (DISPLAY_VER(display) >= 11) {
3788 display->funcs.cdclk = &icl_cdclk_funcs;
3789 display->cdclk.table = icl_cdclk_table;
3790 } else if (display->platform.geminilake || display->platform.broxton) {
3791 display->funcs.cdclk = &bxt_cdclk_funcs;
3792 if (display->platform.geminilake)
3793 display->cdclk.table = glk_cdclk_table;
3795 display->cdclk.table = bxt_cdclk_table;
3796 } else if (DISPLAY_VER(display) == 9) {
3797 display->funcs.cdclk = &skl_cdclk_funcs;
3798 } else if (display->platform.broadwell) {
3799 display->funcs.cdclk = &bdw_cdclk_funcs;
3800 } else if (display->platform.haswell) {
3801 display->funcs.cdclk = &hsw_cdclk_funcs;
3802 } else if (display->platform.cherryview) {
3803 display->funcs.cdclk = &chv_cdclk_funcs;
3804 } else if (display->platform.valleyview) {
3805 display->funcs.cdclk = &vlv_cdclk_funcs;
3806 } else if (display->platform.sandybridge || display->platform.ivybridge) {
3807 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs;
3808 } else if (display->platform.ironlake) {
3809 display->funcs.cdclk = &ilk_cdclk_funcs;
3810 } else if (display->platform.gm45) {
3811 display->funcs.cdclk = &gm45_cdclk_funcs;
3812 } else if (display->platform.g45) {
3813 display->funcs.cdclk = &g33_cdclk_funcs;
3814 } else if (display->platform.i965gm) {
3815 display->funcs.cdclk = &i965gm_cdclk_funcs;
3816 } else if (display->platform.i965g) {
3817 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs;
3818 } else if (display->platform.pineview) {
3819 display->funcs.cdclk = &pnv_cdclk_funcs;
3820 } else if (display->platform.g33) {
3821 display->funcs.cdclk = &g33_cdclk_funcs;
3822 } else if (display->platform.i945gm) {
3823 display->funcs.cdclk = &i945gm_cdclk_funcs;
3824 } else if (display->platform.i945g) {
3825 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs;
3826 } else if (display->platform.i915gm) {
3827 display->funcs.cdclk = &i915gm_cdclk_funcs;
3828 } else if (display->platform.i915g) {
3829 display->funcs.cdclk = &i915g_cdclk_funcs;
3830 } else if (display->platform.i865g) {
3831 display->funcs.cdclk = &i865g_cdclk_funcs;
3832 } else if (display->platform.i85x) {
3833 display->funcs.cdclk = &i85x_cdclk_funcs;
3834 } else if (display->platform.i845g) {
3835 display->funcs.cdclk = &i845g_cdclk_funcs;
3836 } else if (display->platform.i830) {
3837 display->funcs.cdclk = &i830_cdclk_funcs;
3840 if (drm_WARN(display->drm, !display->funcs.cdclk,
3842 display->funcs.cdclk = &i830_cdclk_funcs;