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Searched refs:csr (Results 1 – 25 of 159) sorted by relevance

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/linux/drivers/crypto/intel/qat/qat_common/
H A Dadf_gen4_ras.c10 static void enable_errsou_reporting(void __iomem *csr) in enable_errsou_reporting() argument
13 ADF_CSR_WR(csr, ADF_GEN4_ERRMSK0, 0); in enable_errsou_reporting()
16 ADF_CSR_WR(csr, ADF_GEN4_ERRMSK1, 0); in enable_errsou_reporting()
22 ADF_CSR_WR(csr, ADF_GEN4_ERRMSK2, in enable_errsou_reporting()
30 ADF_CSR_WR(csr, ADF_GEN4_ERRMSK3, in enable_errsou_reporting()
35 static void disable_errsou_reporting(void __iomem *csr) in disable_errsou_reporting() argument
40 ADF_CSR_WR(csr, ADF_GEN4_ERRMSK0, ADF_GEN4_ERRSOU0_BIT); in disable_errsou_reporting()
43 ADF_CSR_WR(csr, ADF_GEN4_ERRMSK1, ADF_GEN4_ERRSOU1_BITMASK); in disable_errsou_reporting()
46 val = ADF_CSR_RD(csr, ADF_GEN4_ERRMSK2); in disable_errsou_reporting()
48 ADF_CSR_WR(csr, ADF_GEN4_ERRMSK2, val); in disable_errsou_reporting()
[all …]
H A Dicp_qat_hw_20_comp.h23 ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER(struct icp_qat_hw_comp_20_config_csr_lower csr) in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER() argument
27 QAT_FIELD_SET(val32, csr.algo, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
30 QAT_FIELD_SET(val32, csr.sd, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
33 QAT_FIELD_SET(val32, csr.edmm, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
36 QAT_FIELD_SET(val32, csr.hbs, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
39 QAT_FIELD_SET(val32, csr.lllbd, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
42 QAT_FIELD_SET(val32, csr.mmctrl, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
45 QAT_FIELD_SET(val32, csr.hash_col, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
48 QAT_FIELD_SET(val32, csr.hash_update, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
51 QAT_FIELD_SET(val32, csr.skip_ctrl, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
[all …]
H A Dicp_qat_hal.h125 #define SET_CAP_CSR(handle, csr, val) \ argument
126 ADF_CSR_WR((handle)->hal_cap_g_ctl_csr_addr_v, csr, val)
127 #define GET_CAP_CSR(handle, csr) \ argument
128 ADF_CSR_RD((handle)->hal_cap_g_ctl_csr_addr_v, csr)
131 #define AE_CSR_ADDR(handle, ae, csr) (AE_CSR(handle, ae) + (0x3ff & (csr))) argument
132 #define SET_AE_CSR(handle, ae, csr, val) \ argument
133 ADF_CSR_WR(AE_CSR_ADDR(handle, ae, csr), 0, val)
134 #define GET_AE_CSR(handle, ae, csr) ADF_CSR_RD(AE_CSR_ADDR(handle, ae, csr), 0) argument
/linux/arch/alpha/kernel/
H A Dcore_tsunami.c181 volatile unsigned long *csr; in tsunami_pci_tbi() local
186 csr = &pchip->tlbia.csr; in tsunami_pci_tbi()
188 csr = &pchip->tlbiv.csr; in tsunami_pci_tbi()
194 *csr = value; in tsunami_pci_tbi()
196 *csr; in tsunami_pci_tbi()
227 TSUNAMI_cchip->misc.csr |= (1L << 28); /* clear NXM... */ in tsunami_probe_write()
231 if (TSUNAMI_cchip->misc.csr & (1L << 28)) { in tsunami_probe_write()
232 int source = (TSUNAMI_cchip->misc.csr >> 29) & 7; in tsunami_probe_write()
233 TSUNAMI_cchip->misc.csr |= (1L << 28); /* ...and unlock NXS. */ in tsunami_probe_write()
251 if (tsunami_probe_read(&pchip->pctl.csr) == 0) in tsunami_init_one_pchip()
[all …]
H A Dcore_wildfire.c121 pci->pci_window[0].wbase.csr = hose->sg_isa->dma_base | 3; in wildfire_init_hose()
122 pci->pci_window[0].wmask.csr = (hose->sg_isa->size - 1) & 0xfff00000; in wildfire_init_hose()
123 pci->pci_window[0].tbase.csr = virt_to_phys(hose->sg_isa->ptes); in wildfire_init_hose()
125 pci->pci_window[1].wbase.csr = 0x40000000 | 1; in wildfire_init_hose()
126 pci->pci_window[1].wmask.csr = (0x40000000 -1) & 0xfff00000; in wildfire_init_hose()
127 pci->pci_window[1].tbase.csr = 0; in wildfire_init_hose()
129 pci->pci_window[2].wbase.csr = 0x80000000 | 1; in wildfire_init_hose()
130 pci->pci_window[2].wmask.csr = (0x40000000 -1) & 0xfff00000; in wildfire_init_hose()
131 pci->pci_window[2].tbase.csr = 0x40000000; in wildfire_init_hose()
133 pci->pci_window[3].wbase.csr = hose->sg_pci->dma_base | 3; in wildfire_init_hose()
[all …]
H A Dcore_titan.c207 volatile unsigned long *csr; in titan_pci_tbi() local
220 csr = &port->port_specific.g.gtlbia.csr; in titan_pci_tbi()
222 csr = &port->port_specific.g.gtlbiv.csr; in titan_pci_tbi()
229 *csr = value; in titan_pci_tbi()
231 *csr; in titan_pci_tbi()
240 pctl.pctl_q_whole = port->pctl.csr; in titan_query_agp()
293 saved_config[index].wsba[0] = port->wsba[0].csr; in titan_init_one_pachip_port()
294 saved_config[index].wsm[0] = port->wsm[0].csr; in titan_init_one_pachip_port()
295 saved_config[index].tba[0] = port->tba[0].csr; in titan_init_one_pachip_port()
297 saved_config[index].wsba[1] = port->wsba[1].csr; in titan_init_one_pachip_port()
[all …]
H A Dsys_marvel.c96 ctl = &io7->csrs->PO7_LSI_CTL[irq & 0xff].csr; /* assume LSI */ in io7_get_irq_ctl()
98 ctl = &io7->csrs->PO7_MSI_CTL[((irq - 0x80) >> 5) & 0x0f].csr; in io7_get_irq_ctl()
174 volatile unsigned long *csr, in io7_redirect_irq() argument
179 val = *csr; in io7_redirect_irq()
183 *csr = val; in io7_redirect_irq()
185 *csr; in io7_redirect_irq()
196 val = io7->csrs->PO7_LSI_CTL[which].csr; in io7_redirect_one_lsi()
200 io7->csrs->PO7_LSI_CTL[which].csr = val; in io7_redirect_one_lsi()
202 io7->csrs->PO7_LSI_CTL[which].csr; in io7_redirect_one_lsi()
213 val = io7->csrs->PO7_MSI_CTL[which].csr; in io7_redirect_one_msi()
[all …]
H A Derr_marvel.c818 err_sum |= io7->csrs->PO7_ERROR_SUM.csr; in marvel_find_io7_with_error()
822 err_sum |= io7->ports[i].csrs->POx_ERR_SUM.csr; in marvel_find_io7_with_error()
843 io->io_asic_rev = io7->csrs->IO_ASIC_REV.csr; in marvel_find_io7_with_error()
844 io->io_sys_rev = io7->csrs->IO_SYS_REV.csr; in marvel_find_io7_with_error()
845 io->io7_uph = io7->csrs->IO7_UPH.csr; in marvel_find_io7_with_error()
846 io->hpi_ctl = io7->csrs->HPI_CTL.csr; in marvel_find_io7_with_error()
847 io->crd_ctl = io7->csrs->CRD_CTL.csr; in marvel_find_io7_with_error()
848 io->hei_ctl = io7->csrs->HEI_CTL.csr; in marvel_find_io7_with_error()
849 io->po7_error_sum = io7->csrs->PO7_ERROR_SUM.csr; in marvel_find_io7_with_error()
850 io->po7_uncrr_sym = io7->csrs->PO7_UNCRR_SYM.csr; in marvel_find_io7_with_error()
[all …]
H A Dcore_marvel.c61 q = ev7csr->csr; in read_ev7_csr()
73 ev7csr->csr = q; in write_ev7_csr()
184 csrs->POx_ERR_SUM.csr = -1UL; in io7_clear_errors()
185 csrs->POx_TLB_ERR.csr = -1UL; in io7_clear_errors()
186 csrs->POx_SPL_COMPLT.csr = -1UL; in io7_clear_errors()
187 csrs->POx_TRANS_SUM.csr = -1UL; in io7_clear_errors()
195 p7csrs->PO7_ERROR_SUM.csr = -1UL; in io7_clear_errors()
196 p7csrs->PO7_UNCRR_SYM.csr = -1UL; in io7_clear_errors()
197 p7csrs->PO7_CRRCT_SYM.csr = -1UL; in io7_clear_errors()
268 io7_port->saved_wbase[i] = csrs->POx_WBASE[i].csr; in io7_init_hose()
[all …]
/linux/arch/sparc/kernel/
H A Debus.c74 u32 csr = 0; in ebus_dma_irq() local
77 csr = readl(p->regs + EBDMA_CSR); in ebus_dma_irq()
78 writel(csr, p->regs + EBDMA_CSR); in ebus_dma_irq()
81 if (csr & EBDMA_CSR_ERR_PEND) { in ebus_dma_irq()
85 } else if (csr & EBDMA_CSR_INT_PEND) { in ebus_dma_irq()
87 (csr & EBDMA_CSR_TC) ? in ebus_dma_irq()
99 u32 csr; in ebus_dma_register() local
113 csr = EBDMA_CSR_BURST_SZ_16 | EBDMA_CSR_EN_CNT; in ebus_dma_register()
116 csr |= EBDMA_CSR_TCI_DIS; in ebus_dma_register()
118 writel(csr, p->regs + EBDMA_CSR); in ebus_dma_register()
[all …]
/linux/arch/loongarch/kvm/
H A Dvcpu.c68 struct loongarch_csrs *csr = vcpu->arch.csr; in kvm_save_guest_pmu() local
70 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_PERFCNTR0); in kvm_save_guest_pmu()
71 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_PERFCNTR1); in kvm_save_guest_pmu()
72 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_PERFCNTR2); in kvm_save_guest_pmu()
73 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_PERFCNTR3); in kvm_save_guest_pmu()
74 kvm_read_clear_hw_gcsr(csr, LOONGARCH_CSR_PERFCTRL0); in kvm_save_guest_pmu()
75 kvm_read_clear_hw_gcsr(csr, LOONGARCH_CSR_PERFCTRL1); in kvm_save_guest_pmu()
76 kvm_read_clear_hw_gcsr(csr, LOONGARCH_CSR_PERFCTRL2); in kvm_save_guest_pmu()
77 kvm_read_clear_hw_gcsr(csr, LOONGARCH_CSR_PERFCTRL3); in kvm_save_guest_pmu()
82 struct loongarch_csrs *csr = vcpu->arch.csr; in kvm_restore_guest_pmu() local
[all …]
H A Dtimer.c46 kvm_write_sw_gcsr(vcpu->arch.csr, LOONGARCH_CSR_TVAL, 0); in kvm_init_timer()
57 struct loongarch_csrs *csr = vcpu->arch.csr; in kvm_restore_timer() local
64 cfg = kvm_read_sw_gcsr(csr, LOONGARCH_CSR_TCFG); in kvm_restore_timer()
67 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_ESTAT); in kvm_restore_timer()
68 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_TCFG); in kvm_restore_timer()
71 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_TVAL); in kvm_restore_timer()
90 ticks = kvm_read_sw_gcsr(csr, LOONGARCH_CSR_TVAL); in kvm_restore_timer()
91 estat = kvm_read_sw_gcsr(csr, LOONGARCH_CSR_ESTAT); in kvm_restore_timer()
142 struct loongarch_csrs *csr = vcpu->arch.csr; in _kvm_save_timer() local
144 cfg = kvm_read_sw_gcsr(csr, LOONGARCH_CSR_TCFG); in _kvm_save_timer()
[all …]
/linux/arch/riscv/kvm/
H A Daia.c72 struct kvm_vcpu_aia_csr *csr = &vcpu->arch.aia_context.guest_csr; in kvm_riscv_vcpu_aia_flush_interrupts() local
82 csr->hviph &= ~mask; in kvm_riscv_vcpu_aia_flush_interrupts()
83 csr->hviph |= val; in kvm_riscv_vcpu_aia_flush_interrupts()
89 struct kvm_vcpu_aia_csr *csr = &vcpu->arch.aia_context.guest_csr; in kvm_riscv_vcpu_aia_sync_interrupts() local
92 csr->vsieh = ncsr_read(CSR_VSIEH); in kvm_riscv_vcpu_aia_sync_interrupts()
126 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; in kvm_riscv_vcpu_aia_update_hvip() local
134 ncsr_write(CSR_HVICTL, aia_hvictl_value(!!(csr->hvip & BIT(IRQ_VS_EXT)))); in kvm_riscv_vcpu_aia_update_hvip()
139 struct kvm_vcpu_aia_csr *csr = &vcpu->arch.aia_context.guest_csr; in kvm_riscv_vcpu_aia_load() local
147 nacl_csr_write(nsh, CSR_VSISELECT, csr->vsiselect); in kvm_riscv_vcpu_aia_load()
148 nacl_csr_write(nsh, CSR_HVIPRIO1, csr->hviprio1); in kvm_riscv_vcpu_aia_load()
[all …]
H A Dvcpu.c51 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; in kvm_riscv_reset_vcpu() local
69 memcpy(csr, reset_csr, sizeof(*csr)); in kvm_riscv_reset_vcpu()
349 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; in kvm_riscv_vcpu_flush_interrupts() local
356 csr->hvip &= ~mask; in kvm_riscv_vcpu_flush_interrupts()
357 csr->hvip |= val; in kvm_riscv_vcpu_flush_interrupts()
368 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; in kvm_riscv_vcpu_sync_interrupts() local
371 csr->vsie = ncsr_read(CSR_VSIE); in kvm_riscv_vcpu_sync_interrupts()
375 if ((csr->hvip ^ hvip) & (1UL << IRQ_VS_SOFT)) { in kvm_riscv_vcpu_sync_interrupts()
388 if ((csr->hvip ^ hvip) & (1UL << IRQ_PMU_OVF)) { in kvm_riscv_vcpu_sync_interrupts()
576 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; in kvm_arch_vcpu_load() local
[all …]
/linux/drivers/watchdog/
H A Dshwdt.c85 u8 csr; in sh_wdt_start() local
95 csr = sh_wdt_read_csr(); in sh_wdt_start()
96 csr |= WTCSR_WT | clock_division_ratio; in sh_wdt_start()
97 sh_wdt_write_csr(csr); in sh_wdt_start()
109 csr = sh_wdt_read_csr(); in sh_wdt_start()
110 csr |= WTCSR_TME; in sh_wdt_start()
111 csr &= ~WTCSR_RSTS; in sh_wdt_start()
112 sh_wdt_write_csr(csr); in sh_wdt_start()
115 csr = sh_wdt_read_rstcsr(); in sh_wdt_start()
116 csr &= ~RSTCSR_RSTS; in sh_wdt_start()
[all …]
/linux/arch/sh/kernel/cpu/
H A Dadc.c16 unsigned char csr; in adc_single() local
22 csr = __raw_readb(ADCSR); in adc_single()
23 csr = channel | ADCSR_ADST | ADCSR_CKS; in adc_single()
24 __raw_writeb(csr, ADCSR); in adc_single()
27 csr = __raw_readb(ADCSR); in adc_single()
28 } while ((csr & ADCSR_ADF) == 0); in adc_single()
30 csr &= ~(ADCSR_ADF | ADCSR_ADST); in adc_single()
31 __raw_writeb(csr, ADCSR); in adc_single()
/linux/sound/soc/intel/atom/sst/
H A Dsst_loader.c56 union config_status_reg_mrfld csr; in intel_sst_reset_dsp_mrfld() local
59 csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR); in intel_sst_reset_dsp_mrfld()
61 dev_dbg(sst_drv_ctx->dev, "value:0x%llx\n", csr.full); in intel_sst_reset_dsp_mrfld()
63 csr.full |= 0x7; in intel_sst_reset_dsp_mrfld()
64 sst_shim_write64(sst_drv_ctx->shim, SST_CSR, csr.full); in intel_sst_reset_dsp_mrfld()
65 csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR); in intel_sst_reset_dsp_mrfld()
67 dev_dbg(sst_drv_ctx->dev, "value:0x%llx\n", csr.full); in intel_sst_reset_dsp_mrfld()
69 csr.full &= ~(0x1); in intel_sst_reset_dsp_mrfld()
70 sst_shim_write64(sst_drv_ctx->shim, SST_CSR, csr.full); in intel_sst_reset_dsp_mrfld()
72 csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR); in intel_sst_reset_dsp_mrfld()
[all …]
/linux/arch/loongarch/include/asm/
H A Dkvm_csr.h14 #define gcsr_read(csr) \ argument
20 : [reg] "i" (csr) \
25 #define gcsr_write(v, csr) \ argument
31 : [reg] "i" (csr) \
36 #define gcsr_xchg(v, m, csr) \ argument
42 : [mask] "r" (m), [reg] "i" (csr) \
182 #define kvm_save_hw_gcsr(csr, gid) (csr->csrs[gid] = gcsr_read(gid)) argument
183 #define kvm_restore_hw_gcsr(csr, gid) (gcsr_write(csr->csrs[gid], gid)) argument
185 #define kvm_read_clear_hw_gcsr(csr, gid) (csr->csrs[gid] = gcsr_write(0, gid)) argument
189 static __always_inline unsigned long kvm_read_sw_gcsr(struct loongarch_csrs *csr, int gid) in kvm_read_sw_gcsr() argument
[all …]
/linux/drivers/net/pcs/
H A Dpcs-xpcs-plat.c41 static u16 xpcs_mmio_addr_page(ptrdiff_t csr) in xpcs_mmio_addr_page() argument
43 return FIELD_GET(0x1fff00, csr); in xpcs_mmio_addr_page()
46 static ptrdiff_t xpcs_mmio_addr_offset(ptrdiff_t csr) in xpcs_mmio_addr_offset() argument
48 return FIELD_GET(0xff, csr); in xpcs_mmio_addr_offset()
54 ptrdiff_t csr, ofs; in xpcs_mmio_read_reg_indirect() local
58 csr = xpcs_mmio_addr_format(dev, reg); in xpcs_mmio_read_reg_indirect()
59 page = xpcs_mmio_addr_page(csr); in xpcs_mmio_read_reg_indirect()
60 ofs = xpcs_mmio_addr_offset(csr); in xpcs_mmio_read_reg_indirect()
85 ptrdiff_t csr, ofs; in xpcs_mmio_write_reg_indirect() local
89 csr = xpcs_mmio_addr_format(dev, reg); in xpcs_mmio_write_reg_indirect()
[all …]
/linux/drivers/usb/musb/
H A Dmusb_cppi41.c56 u16 csr; in save_rx_toggle() local
64 csr = musb_readw(cppi41_channel->hw_ep->regs, MUSB_RXCSR); in save_rx_toggle()
65 toggle = csr & MUSB_RXCSR_H_DATATOGGLE ? 1 : 0; in save_rx_toggle()
74 u16 csr; in update_rx_toggle() local
83 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); in update_rx_toggle()
84 toggle = csr & MUSB_RXCSR_H_DATATOGGLE ? 1 : 0; in update_rx_toggle()
92 csr |= MUSB_RXCSR_H_DATATOGGLE | MUSB_RXCSR_H_WR_DATATOGGLE; in update_rx_toggle()
93 musb_writew(cppi41_channel->hw_ep->regs, MUSB_RXCSR, csr); in update_rx_toggle()
105 u16 csr; in musb_is_tx_fifo_empty() local
108 csr = musb_readw(epio, MUSB_TXCSR); in musb_is_tx_fifo_empty()
[all …]
H A Dmusbhsdma.c152 u16 csr = 0; in configure_channel() local
158 csr |= 1 << MUSB_HSDMA_MODE1_SHIFT; in configure_channel()
161 csr |= MUSB_HSDMA_BURSTMODE_INCR16 in configure_channel()
164 csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT) in configure_channel()
178 csr); in configure_channel()
228 u16 csr; in dma_channel_abort() local
239 csr = musb_readw(mbase, offset); in dma_channel_abort()
240 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB); in dma_channel_abort()
241 musb_writew(mbase, offset, csr); in dma_channel_abort()
242 csr &= ~MUSB_TXCSR_DMAMODE; in dma_channel_abort()
[all …]
/linux/drivers/pcmcia/
H A Dpxa2xx_sharpsl.c57 unsigned short cpr, csr; in sharpsl_pcmcia_socket_state() local
65 csr = read_scoop_reg(scoop, SCOOP_CSR); in sharpsl_pcmcia_socket_state()
66 if (csr & 0x0004) { in sharpsl_pcmcia_socket_state()
74 csr |= SCOOP_DEV[skt->nr].keep_vs; in sharpsl_pcmcia_socket_state()
79 SCOOP_DEV[skt->nr].keep_vs = (csr & 0x00C0); in sharpsl_pcmcia_socket_state()
90 state->detect = (csr & 0x0004) ? 0 : 1; in sharpsl_pcmcia_socket_state()
91 state->ready = (csr & 0x0002) ? 1 : 0; in sharpsl_pcmcia_socket_state()
92 state->bvd1 = (csr & 0x0010) ? 1 : 0; in sharpsl_pcmcia_socket_state()
93 state->bvd2 = (csr & 0x0020) ? 1 : 0; in sharpsl_pcmcia_socket_state()
94 state->wrprot = (csr & 0x0008) ? 1 : 0; in sharpsl_pcmcia_socket_state()
[all …]
/linux/arch/mips/dec/
H A Dkn02-irq.c30 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + in unmask_kn02_irq() local
34 *csr = cached_kn02_csr; in unmask_kn02_irq()
39 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + in mask_kn02_irq() local
43 *csr = cached_kn02_csr; in mask_kn02_irq()
62 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + in init_kn02_irqs() local
68 *csr = cached_kn02_csr; in init_kn02_irqs()
/linux/arch/mips/kernel/
H A Dsignal.c75 uint32_t __user *csr = sc + abi->off_sc_fpc_csr; in copy_fp_to_sigcontext() local
85 err |= __put_user(current->thread.fpu.fcr31, csr); in copy_fp_to_sigcontext()
94 uint32_t __user *csr = sc + abi->off_sc_fpc_csr; in copy_fp_from_sigcontext() local
104 err |= __get_user(current->thread.fpu.fcr31, csr); in copy_fp_from_sigcontext()
130 uint32_t __user *csr = sc + abi->off_sc_fpc_csr; in save_hw_fp_context() local
132 return _save_fp_context(fpregs, csr); in save_hw_fp_context()
139 uint32_t __user *csr = sc + abi->off_sc_fpc_csr; in restore_hw_fp_context() local
141 return _restore_fp_context(fpregs, csr); in restore_hw_fp_context()
188 err = __put_user(read_msa_csr(), &msa->csr); in save_msa_extcontext()
195 err = __put_user(current->thread.fpu.msacsr, &msa->csr); in save_msa_extcontext()
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/linux/drivers/usb/mtu3/
H A Dmtu3_gadget_ep0.c139 u32 csr; in ep0_stall_set() local
142 csr = mtu3_readl(mbase, U3D_EP0CSR) & EP0_W1C_BITS; in ep0_stall_set()
144 csr |= EP0_SENDSTALL | pktrdy; in ep0_stall_set()
146 csr = (csr & ~EP0_SENDSTALL) | EP0_SENTSTALL; in ep0_stall_set()
147 mtu3_writel(mtu->mac_base, U3D_EP0CSR, csr); in ep0_stall_set()
515 u32 csr; in ep0_rx_state() local
520 csr = mtu3_readl(mbase, U3D_EP0CSR) & EP0_W1C_BITS; in ep0_rx_state()
537 csr |= EP0_RXPKTRDY; in ep0_rx_state()
545 csr |= EP0_DATAEND; in ep0_rx_state()
550 csr |= EP0_RXPKTRDY | EP0_SENDSTALL; in ep0_rx_state()
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