61 	q = ev7csr->csr;  in read_ev7_csr()
73 	ev7csr->csr = q;  in write_ev7_csr()
184 		csrs->POx_ERR_SUM.csr = -1UL;  in io7_clear_errors()
185 		csrs->POx_TLB_ERR.csr = -1UL;  in io7_clear_errors()
186 		csrs->POx_SPL_COMPLT.csr = -1UL;  in io7_clear_errors()
187 		csrs->POx_TRANS_SUM.csr = -1UL;  in io7_clear_errors()
195 	p7csrs->PO7_ERROR_SUM.csr = -1UL;  in io7_clear_errors()
196 	p7csrs->PO7_UNCRR_SYM.csr = -1UL;  in io7_clear_errors()
197 	p7csrs->PO7_CRRCT_SYM.csr = -1UL;  in io7_clear_errors()
268 		io7_port->saved_wbase[i] = csrs->POx_WBASE[i].csr;  in io7_init_hose()
269 		io7_port->saved_wmask[i] = csrs->POx_WMASK[i].csr;  in io7_init_hose()
270 		io7_port->saved_tbase[i] = csrs->POx_TBASE[i].csr;  in io7_init_hose()
292 	csrs->POx_WBASE[0].csr =   in io7_init_hose()
294 	csrs->POx_WMASK[0].csr = (hose->sg_isa->size - 1) & wbase_m_addr;  in io7_init_hose()
295 	csrs->POx_TBASE[0].csr = virt_to_phys(hose->sg_isa->ptes);  in io7_init_hose()
300 	csrs->POx_WBASE[1].csr = __direct_map_base | wbase_m_ena;  in io7_init_hose()
301 	csrs->POx_WMASK[1].csr = (__direct_map_size - 1) & wbase_m_addr;  in io7_init_hose()
302 	csrs->POx_TBASE[1].csr = 0;  in io7_init_hose()
309 	csrs->POx_WBASE[2].csr =   in io7_init_hose()
311 	csrs->POx_WMASK[2].csr = (hose->sg_pci->size - 1) & wbase_m_addr;  in io7_init_hose()
312 	csrs->POx_TBASE[2].csr = virt_to_phys(hose->sg_pci->ptes);  in io7_init_hose()
317 	csrs->POx_WBASE[3].csr = 0;  in io7_init_hose()
322 	csrs->POx_CTRL.csr &= ~(1UL << 61);  in io7_init_hose()
326 	csrs->POx_MSK_HEI.csr &= ~(3UL << 14);  in io7_init_hose()
351 		if (csrs->POx_CACHE_CTL.csr == 8) {  in marvel_init_io7()
612 	csrs->POx_SG_TBIA.csr = 0;  in marvel_pci_tbi()
614 	csrs->POx_SG_TBIA.csr;  in marvel_pci_tbi()
923 	agp_pll = io7->csrs->POx_RST[IO7_AGP_PORT].csr;  in marvel_agp_configure()
969 	csrs->AGP_CMD.csr = agp->mode.lw;  in marvel_agp_configure()
1090 	agp->capability.lw = csrs->AGP_STAT.csr;  in marvel_agp_info()
1096 	agp->mode.lw = csrs->AGP_CMD.csr;  in marvel_agp_info()