139 	u32 csr;  in ep0_stall_set()  local
142 	csr = mtu3_readl(mbase, U3D_EP0CSR) & EP0_W1C_BITS;  in ep0_stall_set()
144 		csr |= EP0_SENDSTALL | pktrdy;  in ep0_stall_set()
146 		csr = (csr & ~EP0_SENDSTALL) | EP0_SENTSTALL;  in ep0_stall_set()
147 	mtu3_writel(mtu->mac_base, U3D_EP0CSR, csr);  in ep0_stall_set()
515 	u32 csr;  in ep0_rx_state()  local
520 	csr = mtu3_readl(mbase, U3D_EP0CSR) & EP0_W1C_BITS;  in ep0_rx_state()
537 		csr |= EP0_RXPKTRDY;  in ep0_rx_state()
545 			csr |= EP0_DATAEND;  in ep0_rx_state()
550 		csr |= EP0_RXPKTRDY | EP0_SENDSTALL;  in ep0_rx_state()
554 	mtu3_writel(mbase, U3D_EP0CSR, csr);  in ep0_rx_state()
567 	u32 csr;  in ep0_tx_state()  local
596 	csr = mtu3_readl(mtu->mac_base, U3D_EP0CSR) & EP0_W1C_BITS;  in ep0_tx_state()
597 	mtu3_writel(mtu->mac_base, U3D_EP0CSR, csr | EP0_TXPKTRDY);  in ep0_tx_state()
607 	u32 csr;  in ep0_read_setup()  local
609 	csr = mtu3_readl(mtu->mac_base, U3D_EP0CSR) & EP0_W1C_BITS;  in ep0_read_setup()
628 			csr | EP0_SETUPPKTRDY | EP0_DPHTX);  in ep0_read_setup()
632 			(csr | EP0_SETUPPKTRDY) & (~EP0_DPHTX));  in ep0_read_setup()
702 	u32 csr;  in mtu3_ep0_isr()  local
717 	csr = mtu3_readl(mbase, U3D_EP0CSR);  in mtu3_ep0_isr()
719 	dev_dbg(mtu->dev, "%s csr=0x%x\n", __func__, csr);  in mtu3_ep0_isr()
722 	if (csr & EP0_SENTSTALL) {  in mtu3_ep0_isr()
724 		csr = mtu3_readl(mbase, U3D_EP0CSR);  in mtu3_ep0_isr()
733 		if ((csr & EP0_FIFOFULL) == 0) {  in mtu3_ep0_isr()
740 		if (csr & EP0_RXPKTRDY) {  in mtu3_ep0_isr()
747 			(csr & EP0_W1C_BITS) | EP0_DATAEND);  in mtu3_ep0_isr()
758 		if (!(csr & EP0_SETUPPKTRDY))  in mtu3_ep0_isr()