Lines Matching refs:csr
181 volatile unsigned long *csr; in tsunami_pci_tbi() local
186 csr = &pchip->tlbia.csr; in tsunami_pci_tbi()
188 csr = &pchip->tlbiv.csr; in tsunami_pci_tbi()
194 *csr = value; in tsunami_pci_tbi()
196 *csr; in tsunami_pci_tbi()
227 TSUNAMI_cchip->misc.csr |= (1L << 28); /* clear NXM... */ in tsunami_probe_write()
231 if (TSUNAMI_cchip->misc.csr & (1L << 28)) { in tsunami_probe_write()
232 int source = (TSUNAMI_cchip->misc.csr >> 29) & 7; in tsunami_probe_write()
233 TSUNAMI_cchip->misc.csr |= (1L << 28); /* ...and unlock NXS. */ in tsunami_probe_write()
251 if (tsunami_probe_read(&pchip->pctl.csr) == 0) in tsunami_init_one_pchip()
294 saved_config[index].wsba[0] = pchip->wsba[0].csr; in tsunami_init_one_pchip()
295 saved_config[index].wsm[0] = pchip->wsm[0].csr; in tsunami_init_one_pchip()
296 saved_config[index].tba[0] = pchip->tba[0].csr; in tsunami_init_one_pchip()
298 saved_config[index].wsba[1] = pchip->wsba[1].csr; in tsunami_init_one_pchip()
299 saved_config[index].wsm[1] = pchip->wsm[1].csr; in tsunami_init_one_pchip()
300 saved_config[index].tba[1] = pchip->tba[1].csr; in tsunami_init_one_pchip()
302 saved_config[index].wsba[2] = pchip->wsba[2].csr; in tsunami_init_one_pchip()
303 saved_config[index].wsm[2] = pchip->wsm[2].csr; in tsunami_init_one_pchip()
304 saved_config[index].tba[2] = pchip->tba[2].csr; in tsunami_init_one_pchip()
306 saved_config[index].wsba[3] = pchip->wsba[3].csr; in tsunami_init_one_pchip()
307 saved_config[index].wsm[3] = pchip->wsm[3].csr; in tsunami_init_one_pchip()
308 saved_config[index].tba[3] = pchip->tba[3].csr; in tsunami_init_one_pchip()
335 pchip->wsba[0].csr = hose->sg_isa->dma_base | 3; in tsunami_init_one_pchip()
336 pchip->wsm[0].csr = (hose->sg_isa->size - 1) & 0xfff00000; in tsunami_init_one_pchip()
337 pchip->tba[0].csr = virt_to_phys(hose->sg_isa->ptes); in tsunami_init_one_pchip()
339 pchip->wsba[1].csr = hose->sg_pci->dma_base | 3; in tsunami_init_one_pchip()
340 pchip->wsm[1].csr = (hose->sg_pci->size - 1) & 0xfff00000; in tsunami_init_one_pchip()
341 pchip->tba[1].csr = virt_to_phys(hose->sg_pci->ptes); in tsunami_init_one_pchip()
343 pchip->wsba[2].csr = 0x80000000 | 1; in tsunami_init_one_pchip()
344 pchip->wsm[2].csr = (0x80000000 - 1) & 0xfff00000; in tsunami_init_one_pchip()
345 pchip->tba[2].csr = 0; in tsunami_init_one_pchip()
347 pchip->wsba[3].csr = 0; in tsunami_init_one_pchip()
350 pchip->pctl.csr |= pctl_m_mwin; in tsunami_init_one_pchip()
396 printk("%s: CSR_CSC 0x%lx\n", __func__, TSUNAMI_cchip->csc.csr); in tsunami_init_arch()
397 printk("%s: CSR_MTR 0x%lx\n", __func__, TSUNAMI_cchip.mtr.csr); in tsunami_init_arch()
398 printk("%s: CSR_MISC 0x%lx\n", __func__, TSUNAMI_cchip->misc.csr); in tsunami_init_arch()
399 printk("%s: CSR_DIM0 0x%lx\n", __func__, TSUNAMI_cchip->dim0.csr); in tsunami_init_arch()
400 printk("%s: CSR_DIM1 0x%lx\n", __func__, TSUNAMI_cchip->dim1.csr); in tsunami_init_arch()
401 printk("%s: CSR_DIR0 0x%lx\n", __func__, TSUNAMI_cchip->dir0.csr); in tsunami_init_arch()
402 printk("%s: CSR_DIR1 0x%lx\n", __func__, TSUNAMI_cchip->dir1.csr); in tsunami_init_arch()
403 printk("%s: CSR_DRIR 0x%lx\n", __func__, TSUNAMI_cchip->drir.csr); in tsunami_init_arch()
406 printk("%s: CSR_DSC 0x%lx\n", __func__, TSUNAMI_dchip->dsc.csr); in tsunami_init_arch()
407 printk("%s: CSR_STR 0x%lx\n", __func__, TSUNAMI_dchip->str.csr); in tsunami_init_arch()
408 printk("%s: CSR_DREV 0x%lx\n", __func__, TSUNAMI_dchip->drev.csr); in tsunami_init_arch()
417 if (TSUNAMI_cchip->csc.csr & 1L<<14) in tsunami_init_arch()
427 pchip->wsba[0].csr = saved_config[index].wsba[0]; in tsunami_kill_one_pchip()
428 pchip->wsm[0].csr = saved_config[index].wsm[0]; in tsunami_kill_one_pchip()
429 pchip->tba[0].csr = saved_config[index].tba[0]; in tsunami_kill_one_pchip()
431 pchip->wsba[1].csr = saved_config[index].wsba[1]; in tsunami_kill_one_pchip()
432 pchip->wsm[1].csr = saved_config[index].wsm[1]; in tsunami_kill_one_pchip()
433 pchip->tba[1].csr = saved_config[index].tba[1]; in tsunami_kill_one_pchip()
435 pchip->wsba[2].csr = saved_config[index].wsba[2]; in tsunami_kill_one_pchip()
436 pchip->wsm[2].csr = saved_config[index].wsm[2]; in tsunami_kill_one_pchip()
437 pchip->tba[2].csr = saved_config[index].tba[2]; in tsunami_kill_one_pchip()
439 pchip->wsba[3].csr = saved_config[index].wsba[3]; in tsunami_kill_one_pchip()
440 pchip->wsm[3].csr = saved_config[index].wsm[3]; in tsunami_kill_one_pchip()
441 pchip->tba[3].csr = saved_config[index].tba[3]; in tsunami_kill_one_pchip()
448 if (TSUNAMI_cchip->csc.csr & 1L<<14) in tsunami_kill_arch()
455 pchip->perror.csr; in tsunami_pci_clr_err_1()
456 pchip->perror.csr = 0x040; in tsunami_pci_clr_err_1()
458 pchip->perror.csr; in tsunami_pci_clr_err_1()
467 if (TSUNAMI_cchip->csc.csr & 1L<<14) in tsunami_pci_clr_err()