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Searched refs:VECS0 (Results 1 – 16 of 16) sorted by relevance

/linux/drivers/gpu/drm/i915/
H A Di915_pci.c388 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
447 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
453 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
498 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
513 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
560 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
581 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
614 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
620 .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
627 .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
[all …]
H A Di915_drv.h618 ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)
H A Di915_gpu_error.c1311 case VECS0: in engine_record_registers()
/linux/drivers/gpu/drm/i915/gvt/
H A Dmmio_context.c143 {VECS0, RING_EXCC(VEBOX_RING_BASE), 0xffff, false}, /* 0x1a028 */
171 [VECS0] = 0xcb00,
358 [VECS0] = 0x4270,
415 [VECS0] = 0xcb00, in switch_mocs()
H A Dexeclist.c53 [VECS0] = VECS_AS_CONTEXT_SWITCH,
H A Dcmd_parser.c431 #define R_VECS BIT(VECS0)
631 [VECS0] = {
1173 [VECS0] = {
H A Dhandlers.c347 engine_mask |= BIT(VECS0); in gdrst_mmio_write()
2110 id = VECS0; in gvt_reg_tlb_control_handler()
/linux/drivers/gpu/drm/i915/gt/
H A Dintel_engine_types.h132 VECS0, enumerator
136 #define _VECS(n) (VECS0 + (n))
H A Dintel_engine_user.c168 [VIDEO_ENHANCEMENT_CLASS] = { VECS0, I915_MAX_VECS }, in legacy_ring_idx()
H A Dintel_engine_cs.c193 [VECS0] = {
420 [VECS0] = GEN11_GRDOM_VECS, in get_reset_domain()
439 [VECS0] = GEN6_GRDOM_VECS, in get_reset_domain()
1714 [VECS0] = MSG_IDLE_VECS0, in __cs_pending_mi_force_wakes()
H A Dintel_mocs.c573 [VECS0] = __GEN9_VECS0_MOCS0, in mocs_offset()
H A Dgen8_engine_cs.c179 case VECS0: in gen12_get_aux_inv_reg()
H A Dintel_ring_submission.c103 case VECS0: in set_hwsp()
H A Dintel_rps.c1934 intel_engine_cs_irq(gt->engine[VECS0], pm_iir >> 10); in gen6_rps_irq_handler()
H A Dintel_execlists_submission.c3497 [VECS0] = GEN8_VECS_IRQ_SHIFT, in logical_ring_default_irqs()
/linux/drivers/gpu/drm/i915/gem/
H A Di915_gem_execbuffer.c2476 [I915_EXEC_VEBOX] = VECS0