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Searched refs:VCS0 (Results 1 – 17 of 17) sorted by relevance

/linux/drivers/gpu/drm/i915/
H A Di915_pci.c225 .platform_engine_mask = BIT(RCS0) | BIT(VCS0),
233 .platform_engine_mask = BIT(RCS0) | BIT(VCS0),
239 .platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
265 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
313 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
380 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
388 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
447 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
453 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
498 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
[all …]
H A Di915_drv.h616 ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
H A Di915_irq.c1074 intel_engine_cs_irq(to_gt(dev_priv)->engine[VCS0], in i965_irq_handler()
H A Di915_gpu_error.c1308 case VCS0: in engine_record_registers()
/linux/drivers/gpu/drm/i915/gt/
H A Dintel_engine_types.h123 VCS0, enumerator
131 #define _VCS(n) (VCS0 + (n))
H A Dintel_engine_user.c167 [VIDEO_DECODE_CLASS] = { VCS0, I915_MAX_VCS }, in legacy_ring_idx()
H A Dintel_engine_cs.c134 [VCS0] = {
412 [VCS0] = GEN11_GRDOM_MEDIA, in get_reset_domain()
437 [VCS0] = GEN6_GRDOM_MEDIA, in get_reset_domain()
1706 [VCS0] = MSG_IDLE_VCS0, in __cs_pending_mi_force_wakes()
H A Dintel_mocs.c571 [VCS0] = __GEN9_VCS0_MOCS0, in mocs_offset()
H A Dgen8_engine_cs.c175 case VCS0: in gen12_get_aux_inv_reg()
H A Dintel_ring_submission.c100 case VCS0: in set_hwsp()
H A Dintel_execlists_submission.c3495 [VCS0] = GEN8_VCS0_IRQ_SHIFT, in logical_ring_default_irqs()
/linux/drivers/gpu/drm/i915/gvt/
H A Dmmio_context.c168 [VCS0] = 0xc900,
355 [VCS0] = 0x4264,
412 [VCS0] = 0xc900, in switch_mocs()
H A Dexeclist.c51 [VCS0] = VCS_AS_CONTEXT_SWITCH,
H A Dcmd_parser.c427 #define R_VCS1 BIT(VCS0)
609 [VCS0] = {
1163 [VCS0] = {
H A Dhandlers.c339 engine_mask |= BIT(VCS0); in gdrst_mmio_write()
2101 id = VCS0; in gvt_reg_tlb_control_handler()
/linux/drivers/gpu/drm/i915/gt/uc/
H A Dintel_huc.c275 return __ENGINE_INSTANCES_MASK(mask, VCS0, I915_MAX_VCS); in vcs_supported()
/linux/drivers/gpu/drm/i915/gem/
H A Di915_gem_execbuffer.c2475 [I915_EXEC_BSD] = VCS0,