Searched refs:SME (Results 1 – 6 of 6) sorted by relevance
6 order to support use of the ARM Scalable Matrix Extension (SME).11 included in SME.13 This document does not aim to describe the SME architecture or programmer's15 model features for SME is included in Appendix A.24 * The presence of SME is reported to userspace via HWCAP2_SME in the aux vector25 AT_HWCAP2 entry. Presence of this flag implies the presence of the SME27 described in this document. SME is reported in /proc/cpuinfo as "sme".34 * Support for the execution of SME instructions in userspace can also be36 instruction, and checking that the value of the SME field is nonzero. [3]42 * There are a number of optional SME features, presence of these is reported[all …]
47 Kernel support for temperature and fan monitoring on Sun SME
179 bit 17 - Partial or empty SME or SVE predicate (FEAT_SPEv1p1)180 bit 18 - Empty SME or SVE predicate (FEAT_SPEv1p1)200 their related feature is not present (e.g. SME). For example, if FEAT_SPEv1p2 is
95 #define SME BIT(0) /* SCL Mask Enable */ macro250 u32 icccr2 = CDFD | HLSE | SME; in rcar_i2c_init()
25 * AMD processor with SEV-SNP. Hyper-V does not run guest VMs with AMD SME,
978 # AMD encrypted memory capabilities (SME/SEV)