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Searched refs:SDRAM (Results 1 – 25 of 44) sorted by relevance

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/linux/arch/arm/mach-pxa/
H A Dsleep.S55 @ prepare SDRAM refresh settings
59 @ enable SDRAM self-refresh mode
96 @ prepare SDRAM refresh settings
100 @ enable SDRAM self-refresh mode
107 @ We keep the change-down close to the actual suspend on SDRAM
160 @ external accesses after SDRAM is put in self-refresh mode
166 @ put SDRAM into self-refresh
/linux/Documentation/devicetree/bindings/arm/altera/
H A Dsocfpga-sdram-edac.txt1 Altera SOCFPGA SDRAM Error Detection & Correction [EDAC]
2 The EDAC accesses a range of registers in the SDRAM controller.
7 - interrupts : Should contain the SDRAM ECC IRQ in the
/linux/Documentation/driver-api/memory-devices/
H A Dti-emif.rst4 TI EMIF SDRAM Controller Driver
29 SoCs. EMIF is an SDRAM controller that, based on its revision,
30 supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
/linux/Documentation/devicetree/bindings/arm/omap/
H A Ddmm.txt4 SDRAM controllers (called EMIFs on OMAP). DMM manages various aspects of memory
5 accesses such as priority generation amongst initiators, configuration of SDRAM
/linux/Documentation/devicetree/bindings/memory-controllers/ti/
H A Demif.txt1 * EMIF family of TI SDRAM controllers
3 EMIF - External Memory Interface - is an SDRAM controller used in
57 has capability for generating SDRAM temperature alerts
/linux/drivers/video/fbdev/omap/
H A DKconfig42 bool "Set DMA SDRAM access priority high"
46 (SDRAM) this will speed up graphics DMA operations.
/linux/arch/arm/mach-lpc32xx/
H A Dsuspend.S50 @ Wait for SDRAM busy status to go busy and then idle
/linux/Documentation/devicetree/bindings/clock/
H A Dmvebu-core-clock.txt30 3 = hclk (SDRAM Controller Internal Clock)
31 4 = dclk (SDRAM Interface Clock)
/linux/arch/arm/mach-omap1/
H A Dsleep.S86 @ prepare to put SDRAM into self-refresh manually
156 @ Prepare to put SDRAM into self-refresh manually
/linux/Documentation/arch/arm/stm32/
H A Dstm32f429-overview.rst13 - External memory support through FMC controller (PSRAM, SDRAM, NOR, NAND)
H A Dstm32mp151-overview.rst19 - FMC controller to connect SDRAM, NOR and NAND memories
H A Dstm32h750-overview.rst13 - FMC controller to connect SDRAM, NOR and NAND memories
H A Dstm32mp13-overview.rst19 - FMC controller to connect SDRAM, NOR and NAND memories
H A Dstm32h743-overview.rst13 - FMC controller to connect SDRAM, NOR and NAND memories
H A Dstm32f746-overview.rst13 - FMC controller to connect SDRAM, NOR and NAND memories
H A Dstm32f769-overview.rst13 - FMC controller to connect SDRAM, NOR and NAND memories
/linux/drivers/memory/
H A DKconfig20 Data from JEDEC specs for DDR SDRAM memories,
23 DDR SDRAM controllers.
96 SoCs. EMIF is an SDRAM controller that, based on its revision,
97 supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
/linux/Documentation/admin-guide/perf/
H A Dalibaba_pmu.rst47 satisfying the SDRAM protocol timing requirements, transaction priorities, and
50 to and from the SDRAM. The driveway PMUs have hardware logic to gather
/linux/arch/arm/boot/dts/intel/ixp/
H A Dintel-ixp42x-welltech-epbx100.dts17 /* 64 MB SDRAM */
H A Dintel-ixp42x-netgear-wg302v1.dts19 /* 32 MB SDRAM according to boot arguments */
H A Dintel-ixp42x-gateway-7001.dts19 /* 32 MB SDRAM */
H A Dintel-ixp42x-adi-coyote.dts20 /* CHECKME: 16 MB SDRAM minimum, maybe the Coyote actually has more */
/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2p-ca9.dts245 /* DDR2 SDRAM and Test Chip DDR2 I/O supply */
254 /* DDR2 SDRAM VTT termination voltage */
/linux/drivers/video/fbdev/aty/
H A Dmach64_ct.c354 else if (par->ram_type >= SDRAM) in aty_set_pll_ct()
469 case SDRAM: in aty_init_pll_ct()
557 if (M64_HAS(SDRAM_MAGIC_PLL) && (par->ram_type >= SDRAM)) in aty_init_pll_ct()
/linux/Documentation/fb/
H A Dmatroxfb.rst174 - 0 -> 2x512Kx16 SDRAM, 16/32MB
178 - 3 -> 4x512Kx32 SDRAM, 32MB
180 - 5 -> 2x1Mx32 SDRAM, 32MB
195 sdram tells to driver that you have Gxx0 with SDRAM memory.
319 - Gxx0 SGRAM/SDRAM is not autodetected.

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