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Searched refs:PLL (Results 1 – 25 of 112) sorted by relevance

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/linux/drivers/clk/mediatek/
H A Dclk-mt8195-apmixedsys.c32 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ macro
61 PLL(CLK_APMIXED_NNAPLL, "nnapll", 0x0390, 0x03a0, 0,
63 PLL(CLK_APMIXED_RESPLL, "respll", 0x0190, 0x0320, 0,
65 PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x0360, 0x0370, 0,
67 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0710, 0x0720, 0,
69 PLL(CLK_APMIXED_TVDPLL1, "tvdpll1", 0x00a0, 0x00b0, 0,
71 PLL(CLK_APMIXED_TVDPLL2, "tvdpll2", 0x00c0, 0x00d0, 0,
73 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x00e0, 0x00f0, 0xff000000,
75 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x01d0, 0x01e0, 0xff000000,
77 PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x0890, 0x08a0, 0,
[all …]
H A Dclk-mt8188-apmixedsys.c31 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ macro
60 PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x044C, 0x0458, 0,
62 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0514, 0x0520, 0,
64 PLL(CLK_APMIXED_TVDPLL1, "tvdpll1", 0x0524, 0x0530, 0,
66 PLL(CLK_APMIXED_TVDPLL2, "tvdpll2", 0x0534, 0x0540, 0,
68 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0544, 0x0550, 0xff000000,
70 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x045C, 0x0468, 0xff000000,
72 PLL(CLK_APMIXED_IMGPLL, "imgpll", 0x0554, 0x0560, 0,
74 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0504, 0x0510, 0xff000000,
76 PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x042C, 0x0438, 0,
[all …]
H A Dclk-mt7986-apmixed.c35 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ macro
42 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x0, PLL_AO, 32,
44 PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x0, 0, 32,
46 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x0, 0, 32,
48 PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023c, 0x0, 0, 32,
50 PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024c, 0x0, 0,
52 PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0250, 0x025c, 0x0, 0, 32,
54 PLL(CLK_APMIXED_MPLL, "mpll", 0x0260, 0x0270, 0x0, 0, 32, 0x0260,
56 PLL(CLK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x0, 0, 32,
H A Dclk-mt7981-apmixed.c37 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ macro
44 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, PLL_AO,
46 PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x00000001, 0, 32,
48 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x00000001, 0, 32,
50 PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023C, 0x00000001, 0, 32,
52 PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024C, 0x00000001, 0, 32,
54 PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0250, 0x025C, 0x00000001, 0, 32,
56 PLL(CLK_APMIXED_MPLL, "mpll", 0x0260, 0x0270, 0x00000001, 0, 32,
58 PLL(CLK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x00000001, 0, 32,
H A Dclk-mt6735-apmixedsys.c47 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _rst_bar_mask, \ macro
69 …PLL(CLK_APMIXED_ARMPLL, "armpll", ARMPLL_CON0, ARMPLL_PWR_CON0, 0x00000001, 0, ARMPLL_CON1, 24, 0,…
70 …PLL(CLK_APMIXED_MAINPLL, "mainpll", MAINPLL_CON0, MAINPLL_PWR_CON0, 0xf0000101, CON0_RST_BAR, MAIN…
71 …PLL(CLK_APMIXED_UNIVPLL, "univpll", UNIVPLL_CON0, UNIVPLL_PWR_CON0, 0xfc000001, CON0_RST_BAR, UNIV…
72 …PLL(CLK_APMIXED_MMPLL, "mmpll", MMPLL_CON0, MMPLL_PWR_CON0, 0x00000001, 0, MMPLL_CON1, 24, 0, 0, 0…
73 …PLL(CLK_APMIXED_MSDCPLL, "msdcpll", MSDCPLL_CON0, MSDCPLL_PWR_CON0, 0x00000001, 0, MSDCPLL_CON1, 2…
74 …PLL(CLK_APMIXED_VENCPLL, "vencpll", VENCPLL_CON0, VENCPLL_PWR_CON0, 0x00000001, CON0_RST_BAR, VENC…
75 …PLL(CLK_APMIXED_TVDPLL, "tvdpll", TVDPLL_CON0, TVDPLL_PWR_CON0, 0x00000001, 0, TVDPLL_CON1, 24, 0,…
76 …PLL(CLK_APMIXED_APLL1, "apll1", APLL1_CON0, APLL1_PWR_CON0, 0x00000001, 0, APLL1_CON0, 4, APLL1_CO…
77 …PLL(CLK_APMIXED_APLL2, "apll2", APLL2_CON0, APLL2_PWR_CON0, 0x00000001, 0, APLL2_CON0, 4, APLL2_CO…
H A Dclk-mt2701.c920 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ macro
939 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x200, 0x20c, 0x80000000,
941 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x210, 0x21c, 0xf0000000,
943 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x220, 0x22c, 0xf3000000,
945 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x230, 0x23c, 0, 0,
947 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x240, 0x24c, 0x00000001, 0,
949 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x250, 0x25c, 0x00000001, 0,
951 PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x270, 0x27c, 0x00000001, 0,
953 PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x280, 0x28c, 0x00000001, 0,
955 PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x290, 0x29c, 0x00000001, 0,
[all …]
H A Dclk-mt6765.c694 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ macro
704 PLL(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x021C, 0x0228, 0,
706 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x020C, 0x0218, 0,
708 PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x022C, 0x0238, 0,
710 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x023C, 0x0248, 0,
713 PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x024C, 0x0258, 0,
715 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x025C, 0x0268, 0,
717 PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x026C, 0x0278, 0,
719 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x027C, 0x0288, 0,
721 PLL(CLK_APMIXED_APLL1, "apll1", 0x028C, 0x029C, 0,
[all …]
/linux/drivers/clk/sophgo/
H A DKconfig14 tristate "Sophgo SG2042 PLL clock support"
17 This driver supports the PLL clock controller on the
20 PLL, DDR PLL 0 and DDR PLL 1 respectively.
27 Sophgo SG2042 SoC. This clock IP depends on SG2042 PLL clock
28 because it uses PLL clocks as input.
46 SoC. This controller requires mulitple PLL clock as input.
47 This clock control provides PLL clocks and common clock function
51 tristate "Sophgo SG2044 PLL clock controller support"
56 This driver supports the PLL clock controller on the Sophgo
58 This clock control provides PLL clocks on the SoC.
/linux/Documentation/devicetree/bindings/clock/ti/davinci/
H A Dpll.txt1 Binding for TI DaVinci PLL Controllers
3 The PLL provides clocks to most of the components on the SoC. In addition
4 to the PLL itself, this controller also contains bypasses, gates, dividers,
26 Describes the main PLL clock output (before POSTDIV). The node name must
41 Describes the AUXCLK output of the PLL. The node name must be "auxclk".
48 Describes the OBSCLK output of the PLL. The node name must be "obsclk".
/linux/Documentation/devicetree/bindings/clock/
H A Dvt8500.txt9 "via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock
10 "wm,wm8650-pll-clock" - for a WM8650 PLL clock
11 "wm,wm8750-pll-clock" - for a WM8750 PLL clock
12 "wm,wm8850-pll-clock" - for a WM8850 PLL clock
15 Required properties for PLL clocks:
H A Daxs10x-i2s-pll-clock.txt1 Binding for the AXS10X I2S PLL clock
9 - reg : address and length of the I2S PLL register set.
10 - clocks: shall be the input parent clock phandle for the PLL.
H A Dsnps,pll-clock.txt1 Binding for the AXS10X Generic PLL clock
11 - reg: should always contain 2 pairs address - length: first for PLL config
13 - clocks: shall be the input parent clock phandle for the PLL.
H A Dkeystone-pll.txt1 Binding for keystone PLLs. The main PLL IP typically has a multiplier,
2 a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
4 PLL is controlled by a PLL controller registers along with memory mapped
H A Dsnps,hsdk-pll-clock.txt1 Binding for the HSDK Generic PLL clock
13 - clocks: shall be the input parent clock phandle for the PLL.
/linux/Documentation/driver-api/media/drivers/ccs/
H A Dccs.rst69 CCS PLL calculator
72 The CCS PLL calculator is used to compute the PLL configuration, given sensor's
75 PLL calculator isn't entirely trivial. Yet it is relatively simple to use for a
78 The PLL model implemented by the PLL calculator corresponds to MIPI CCS 1.1.
/linux/drivers/clk/meson/
H A DKconfig114 tristate "Amlogic A1 SoC PLL controller support"
120 Support for the PLL clock controller on Amlogic A113L based
121 device, A1 SoC Family. Say Y if you want A1 PLL clock controller
163 tristate "Amlogic C3 PLL clock controller"
171 Support for the PLL clock controller on Amlogic C302X and C308L devices,
208 tristate "S4 SoC PLL clock controllers support"
216 Support for the PLL clock controller on Amlogic S805X2 and S905Y4 devices,
233 tristate "Amlogic T7 SoC PLL controller support"
242 Support for the PLL clock controller on Amlogic A311D2 based
244 Say Y if you want T7 PLL clock controller to work.
/linux/Documentation/admin-guide/media/
H A Dtechnisat.rst58 #) => ``Generic I2C PLL based tuners``
63 #) => ``Generic I2C PLL based tuners``
80 #) => ``Generic I2C PLL based tuners``
85 #) => ``Generic I2C PLL based tuners``
94 #) => ``Generic I2C PLL based tuners``
H A Dfrontend-cardlist.rst13 tuner/PLL chips, and not all combinations are supported. Often
14 the demodulator and tuner/PLL chip are inside a metal box for
87 tua6100 Infineon TUA6100 PLL
131 Digital terrestrial only tuners/PLL
137 dvb-pll Generic I2C PLL based tuners
/linux/Documentation/devicetree/bindings/cpufreq/
H A Dnvidia,tegra124-cpufreq.txt12 - pll_x: Fast PLL clocksource.
13 - pll_p: Auxiliary PLL used during fast PLL rate changes.
/linux/drivers/clk/mstar/
H A DKconfig7 Support for the CPU PLL present on MStar/Sigmastar SoCs.
15 Support for the MPLL PLL and dividers block present on
/linux/Documentation/devicetree/bindings/sound/
H A Dbrcm,cygnus-audio.txt12 - clocks: PLL and leaf clocks used by audio ports
13 - assigned-clocks: PLL and leaf clocks
15 (usually the PLL)
/linux/drivers/media/common/b2c2/
H A Dflexcop-fe-tuner.c41 #if (FE_SUPPORTED(MT312) || FE_SUPPORTED(STV0299)) && FE_SUPPORTED(PLL)
81 #if FE_SUPPORTED(MT312) && FE_SUPPORTED(PLL)
197 #if FE_SUPPORTED(STV0299) && FE_SUPPORTED(PLL)
421 #if FE_SUPPORTED(MT352) && FE_SUPPORTED(PLL)
476 #if FE_SUPPORTED(NXT200X) && FE_SUPPORTED(PLL)
519 #if FE_SUPPORTED(STV0297) && FE_SUPPORTED(PLL)
/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2p-ca15-tc1.dts146 /* CPU PLL reference clock */
164 /* HDLCD PLL reference clock */
182 /* SYS PLL reference clock */
191 /* DDR2 PLL reference clock */
/linux/drivers/clk/samsung/
H A Dclk-exynosautov920.c335 PLL(pll_531x, FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
337 PLL(pll_531x, FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
339 PLL(pll_531x, FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk",
341 PLL(pll_531x, FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk",
343 PLL(pll_531x, FOUT_SHARED4_PLL, "fout_shared4_pll", "oscclk",
345 PLL(pll_531x, FOUT_SHARED5_PLL, "fout_shared5_pll", "oscclk",
347 PLL(pll_531x, FOUT_MMC_PLL, "fout_mmc_pll", "oscclk",
1084 PLL(pll_531x, CLK_FOUT_CPUCL0_PLL, "fout_cpucl0_pll", "oscclk",
1192 PLL(pll_531x, CLK_FOUT_CPUCL1_PLL, "fout_cpucl1_pll", "oscclk",
1294 PLL(pll_531x, CLK_FOUT_CPUCL2_PLL, "fout_cpucl2_pll", "oscclk",
[all …]
H A Dclk-exynos5250.c736 [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
738 [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
740 [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
742 [gpll] = PLL(pll_35xx, CLK_FOUT_GPLL, "fout_gpll", "fin_pll", GPLL_LOCK,
744 [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
746 [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
748 [vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc",

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