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Searched refs:PLL (Results 1 – 25 of 98) sorted by relevance

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/linux/drivers/clk/sophgo/
H A DKconfig14 tristate "Sophgo SG2042 PLL clock support"
17 This driver supports the PLL clock controller on the
20 PLL, DDR PLL 0 and DDR PLL 1 respectively.
27 Sophgo SG2042 SoC. This clock IP depends on SG2042 PLL clock
28 because it uses PLL clocks as input.
46 SoC. This controller requires mulitple PLL clock as input.
47 This clock control provides PLL clocks and common clock function
51 tristate "Sophgo SG2044 PLL clock controller support"
56 This driver supports the PLL clock controller on the Sophgo
58 This clock control provides PLL clocks on the SoC.
/linux/Documentation/devicetree/bindings/clock/ti/davinci/
H A Dpll.txt1 Binding for TI DaVinci PLL Controllers
3 The PLL provides clocks to most of the components on the SoC. In addition
4 to the PLL itself, this controller also contains bypasses, gates, dividers,
26 Describes the main PLL clock output (before POSTDIV). The node name must
41 Describes the AUXCLK output of the PLL. The node name must be "auxclk".
48 Describes the OBSCLK output of the PLL. The node name must be "obsclk".
/linux/Documentation/devicetree/bindings/clock/
H A Dvt8500.txt9 "via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock
10 "wm,wm8650-pll-clock" - for a WM8650 PLL clock
11 "wm,wm8750-pll-clock" - for a WM8750 PLL clock
12 "wm,wm8850-pll-clock" - for a WM8850 PLL clock
15 Required properties for PLL clocks:
H A Daxs10x-i2s-pll-clock.txt1 Binding for the AXS10X I2S PLL clock
9 - reg : address and length of the I2S PLL register set.
10 - clocks: shall be the input parent clock phandle for the PLL.
H A Dsnps,pll-clock.txt1 Binding for the AXS10X Generic PLL clock
11 - reg: should always contain 2 pairs address - length: first for PLL config
13 - clocks: shall be the input parent clock phandle for the PLL.
H A Dkeystone-pll.txt1 Binding for keystone PLLs. The main PLL IP typically has a multiplier,
2 a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
4 PLL is controlled by a PLL controller registers along with memory mapped
H A Dsnps,hsdk-pll-clock.txt1 Binding for the HSDK Generic PLL clock
13 - clocks: shall be the input parent clock phandle for the PLL.
H A Dst,nomadik.txt23 PLL nodes: these nodes represent the two PLLs on the system,
27 Required properties for the two PLL nodes:
/linux/Documentation/driver-api/media/drivers/ccs/
H A Dccs.rst69 CCS PLL calculator
72 The CCS PLL calculator is used to compute the PLL configuration, given sensor's
75 PLL calculator isn't entirely trivial. Yet it is relatively simple to use for a
78 The PLL model implemented by the PLL calculator corresponds to MIPI CCS 1.1.
/linux/Documentation/admin-guide/media/
H A Dtechnisat.rst58 #) => ``Generic I2C PLL based tuners``
63 #) => ``Generic I2C PLL based tuners``
80 #) => ``Generic I2C PLL based tuners``
85 #) => ``Generic I2C PLL based tuners``
94 #) => ``Generic I2C PLL based tuners``
H A Dfrontend-cardlist.rst13 tuner/PLL chips, and not all combinations are supported. Often
14 the demodulator and tuner/PLL chip are inside a metal box for
87 tua6100 Infineon TUA6100 PLL
131 Digital terrestrial only tuners/PLL
137 dvb-pll Generic I2C PLL based tuners
/linux/Documentation/devicetree/bindings/cpufreq/
H A Dnvidia,tegra124-cpufreq.txt12 - pll_x: Fast PLL clocksource.
13 - pll_p: Auxiliary PLL used during fast PLL rate changes.
/linux/Documentation/ABI/testing/
H A Dsysfs-bus-iio-frequency-adf43507 the fractional-N PLL. It is assumed that the algorithm
16 applications, the reference frequency used by the PLL may
21 down the PLL and its RFOut buffers during REFin changes.
/linux/drivers/iio/frequency/
H A DKconfig6 # Phase-Locked Loop (PLL) frequency synthesizers
10 menu "Frequency Synthesizers DDS/PLL"
27 # Phase-Locked Loop (PLL) frequency synthesizers
30 menu "Phase-Locked Loop (PLL) frequency synthesizers"
100 Downconverter with integrated Fractional-N PLL and VCO.
/linux/Documentation/devicetree/bindings/sound/
H A Dbrcm,cygnus-audio.txt12 - clocks: PLL and leaf clocks used by audio ports
13 - assigned-clocks: PLL and leaf clocks
15 (usually the PLL)
/linux/drivers/clk/mstar/
H A DKconfig7 Support for the CPU PLL present on MStar/Sigmastar SoCs.
15 Support for the MPLL PLL and dividers block present on
/linux/drivers/media/common/b2c2/
H A Dflexcop-fe-tuner.c41 #if (FE_SUPPORTED(MT312) || FE_SUPPORTED(STV0299)) && FE_SUPPORTED(PLL)
81 #if FE_SUPPORTED(MT312) && FE_SUPPORTED(PLL)
197 #if FE_SUPPORTED(STV0299) && FE_SUPPORTED(PLL)
421 #if FE_SUPPORTED(MT352) && FE_SUPPORTED(PLL)
476 #if FE_SUPPORTED(NXT200X) && FE_SUPPORTED(PLL)
519 #if FE_SUPPORTED(STV0297) && FE_SUPPORTED(PLL)
/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2p-ca15-tc1.dts146 /* CPU PLL reference clock */
164 /* HDLCD PLL reference clock */
182 /* SYS PLL reference clock */
191 /* DDR2 PLL reference clock */
H A Dvexpress-v2p-ca15_a7.dts257 /* A15 PLL 0 reference clock */
266 /* A15 PLL 1 reference clock */
275 /* A7 PLL 0 reference clock */
284 /* A7 PLL 1 reference clock */
302 /* HDLCD PLL reference clock */
320 /* SYS PLL reference clock */
329 /* DDR2 PLL reference clock */
/linux/Documentation/userspace-api/media/mediactl/
H A Dmedia-types.rst113 consists on a PLL tuning stage that converts radio frequency (RF)
115 internally IF-PLL decoders for audio and video, but older models
119 - IF-PLL video decoder. It receives the IF from a PLL and decodes
123 Those devices use a different I2C address than the tuner PLL.
126 - IF-PLL sound decoder. It receives the IF from a PLL and decodes
130 tuner PLL and should be controlled together with the IF-PLL video
/linux/drivers/clk/starfive/
H A DKconfig25 bool "StarFive JH7110 PLL clock support"
29 Say yes here to support the PLL clock controller on the
/linux/drivers/clk/rockchip/
H A Dclk-rk3368.c130 [apllb] = PLL(pll_rk3066, PLL_APLLB, "apllb", mux_pll_p, 0, RK3368_PLL_CON(0),
132 [aplll] = PLL(pll_rk3066, PLL_APLLL, "aplll", mux_pll_p, 0, RK3368_PLL_CON(4),
134 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK3368_PLL_CON(8),
136 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3368_PLL_CON(12),
138 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3368_PLL_CON(16),
140 [npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3368_PLL_CON(20),
H A Dclk-rk3128.c159 [apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
161 [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
163 [cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
165 [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
H A Dclk-rk3328.c215 [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
218 [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
221 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
224 [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
227 [npll] = PLL(pll_rk3328, PLL_NPLL, "npll", mux_pll_p,
/linux/drivers/clk/samsung/
H A Dclk-artpec8.c179 PLL(pll_1017x, CLK_FOUT_SHARED0_PLL, "fout_pll_shared0", "fin_pll",
181 PLL(pll_1017x, CLK_FOUT_SHARED1_PLL, "fout_pll_shared1", "fin_pll",
183 PLL(pll_1031x, CLK_FOUT_AUDIO_PLL, "fout_pll_audio", "fin_pll",
485 PLL(pll_1017x, CLK_FOUT_CPUCL_PLL, "fout_pll_cpucl", "fin_pll",
653 PLL(pll_1017x, CLK_FOUT_FSYS_PLL, "fout_pll_fsys", "fin_pll",

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