1*6d7489c7SEugeniy PaltsevBinding for the AXS10X Generic PLL clock 2*6d7489c7SEugeniy Paltsev 3*6d7489c7SEugeniy PaltsevThis binding uses the common clock binding[1]. 4*6d7489c7SEugeniy Paltsev 5*6d7489c7SEugeniy Paltsev[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 6*6d7489c7SEugeniy Paltsev 7*6d7489c7SEugeniy PaltsevRequired properties: 8*6d7489c7SEugeniy Paltsev- compatible: should be "snps,axs10x-<name>-pll-clock" 9*6d7489c7SEugeniy Paltsev "snps,axs10x-arc-pll-clock" 10*6d7489c7SEugeniy Paltsev "snps,axs10x-pgu-pll-clock" 11*6d7489c7SEugeniy Paltsev- reg: should always contain 2 pairs address - length: first for PLL config 12*6d7489c7SEugeniy Paltsevregisters and second for corresponding LOCK CGU register. 13*6d7489c7SEugeniy Paltsev- clocks: shall be the input parent clock phandle for the PLL. 14*6d7489c7SEugeniy Paltsev- #clock-cells: from common clock binding; Should always be set to 0. 15*6d7489c7SEugeniy Paltsev 16*6d7489c7SEugeniy PaltsevExample: 17*6d7489c7SEugeniy Paltsev input-clk: input-clk { 18*6d7489c7SEugeniy Paltsev clock-frequency = <33333333>; 19*6d7489c7SEugeniy Paltsev compatible = "fixed-clock"; 20*6d7489c7SEugeniy Paltsev #clock-cells = <0>; 21*6d7489c7SEugeniy Paltsev }; 22*6d7489c7SEugeniy Paltsev 23*6d7489c7SEugeniy Paltsev core-clk: core-clk@80 { 24*6d7489c7SEugeniy Paltsev compatible = "snps,axs10x-arc-pll-clock"; 25*6d7489c7SEugeniy Paltsev reg = <0x80 0x10>, <0x100 0x10>; 26*6d7489c7SEugeniy Paltsev #clock-cells = <0>; 27*6d7489c7SEugeniy Paltsev clocks = <&input-clk>; 28*6d7489c7SEugeniy Paltsev }; 29