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Searched refs:PIPE_B (Results 1 – 20 of 20) sorted by relevance

/linux/drivers/gpu/drm/i915/display/
H A Dintel_vdsc_regs.h33 #define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
49 #define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
66 #define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
69 #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
72 #define _ICL_DSC0_PPS_0(pipe) _PICK_EVEN((pipe) - PIPE_B, \
75 #define _ICL_DSC1_PPS_0(pipe) _PICK_EVEN((pipe) - PIPE_B, \
78 #define _BMG_DSC2_PPS_0(pipe) _PICK_EVEN((pipe) - PIPE_B, \
224 #define ICL_DSC0_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
227 #define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
230 #define ICL_DSC1_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
[all …]
H A Dskl_watermark.c766 .active_pipes = BIT(PIPE_B),
768 [PIPE_B] = BIT(DBUF_S1),
772 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B),
775 [PIPE_B] = BIT(DBUF_S2),
792 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C),
794 [PIPE_B] = BIT(DBUF_S1),
799 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
802 [PIPE_B] = BIT(DBUF_S1),
829 .active_pipes = BIT(PIPE_B),
831 [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2),
[all …]
H A Dintel_display_device.c176 [PIPE_B] = CURSOR_B_OFFSET, \
182 [PIPE_B] = CURSOR_B_OFFSET, \
189 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
196 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
241 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
304 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
393 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
450 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
479 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
504 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
[all …]
H A Dintel_display_limits.h18 PIPE_B, enumerator
35 TRANSCODER_B = PIPE_B,
H A Dintel_display_power_map.c150 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
394 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
473 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
576 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
752 .irq_pipe_mask = BIT(PIPE_B),
918 .irq_pipe_mask = BIT(PIPE_B),
1073 .irq_pipe_mask = BIT(PIPE_B),
1168 .irq_pipe_mask = BIT(PIPE_B),
1344 .irq_pipe_mask = BIT(PIPE_B),
1501 .irq_pipe_mask = BIT(PIPE_B),
[all …]
H A Dintel_display_irq.c411 i915_enable_pipestat(display, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); in i915_enable_asle_pipestat()
565 case PIPE_B: in i9xx_pipestat_irq_ack()
720 intel_pch_fifo_underrun_irq_handler(display, PIPE_B); in ibx_irq_handler()
730 case PIPE_B: in ivb_err_int_pipe_fault_mask()
851 case PIPE_B: in ilk_gtt_fault_pipe_fault_mask()
1354 pipe = PIPE_B; in gen11_dsi_te_interrupt_handler()
1832 case PIPE_B: in vlv_dpinvgtt_pipe_fault_mask()
1992 i915_enable_pipestat(display, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i915_display_irq_postinstall()
2007 i915_enable_pipestat(display, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i965_display_irq_postinstall()
H A Dintel_display_power_well.c1105 if ((intel_de_read(display, TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE) == 0) in i830_pipes_power_well_enable()
1106 i830_enable_pipe(display, PIPE_B); in i830_pipes_power_well_enable()
1112 i830_disable_pipe(display, PIPE_B); in i830_pipes_power_well_disable()
1120 intel_de_read(display, TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE; in i830_pipes_power_well_enabled()
1412 (intel_de_read(display, DPLL(display, PIPE_B)) & DPLL_VCO_ENABLE) == 0) in assert_chv_phy_status()
1539 assert_pll_disabled(display, PIPE_B); in chv_dpio_cmn_power_well_disable()
H A Dicl_dsi.c836 case PIPE_B: in gen11_dsi_configure_transcoder()
1250 if (DISPLAY_VER(display) == 11 && pipe == PIPE_B) in icl_apply_kvmr_pipe_a_wa()
1603 if (DISPLAY_VER(display) == 11 && pipe == PIPE_B && in gen11_dsi_sync_state()
1744 *pipe = PIPE_B; in gen11_dsi_get_hw_state()
H A Dvlv_dsi.c972 TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE; in intel_dsi_get_hw_state()
997 *pipe = port == PORT_A ? PIPE_A : PIPE_B; in intel_dsi_get_hw_state()
1965 encoder->pipe_mask = BIT(PIPE_B); in vlv_dsi_init()
H A Dintel_dmc.c500 MTL_PIPEDMC_GATING_DIS(PIPE_B)); in mtl_pipedmc_clock_gating_wa()
934 PIPE_B_DMC_W2_PTS_CONFIG_SELECT(PIPE_B) | in intel_dmc_load_program()
H A Dintel_lvds.c932 encoder->pipe_mask = BIT(PIPE_B); in intel_lvds_init()
H A Dintel_display.c2053 if (display->platform.cherryview && pipe == PIPE_B) { in valleyview_crtc_enable()
2738 (pipe == PIPE_B || pipe == PIPE_C)) in intel_set_transcoder_timings()
3472 pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D); in joiner_pipes()
3474 pipes = BIT(PIPE_B) | BIT(PIPE_C); in joiner_pipes()
3790 trans_pipe = PIPE_B; in hsw_enabled_transcoders()
8413 intel_de_read(display, CURCNTR(display, PIPE_B)) & MCURSOR_MODE_MASK); in i830_disable_pipe()
H A Dintel_vrr.c367 ((pipe == PIPE_A) || (pipe == PIPE_B))); in intel_vrr_dc_balance_possible()
H A Dintel_psr.c1232 return pipe <= PIPE_B && port <= PORT_B; in dc3co_is_pipe_port_compatible()
1786 to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_B) in _panel_replay_compute_config()
H A Dintel_sdvo.c1859 if (HAS_PCH_IBX(display) && crtc->pipe == PIPE_B) { in intel_disable_sdvo()
H A Dintel_color.c4274 return pipe == PIPE_A || pipe == PIPE_B; in intel_color_crtc_has_3dlut()
/linux/drivers/gpu/drm/i915/gvt/
H A Dhandlers.c914 calc_index(offset, FDI_RX_CTL(PIPE_A), FDI_RX_CTL(PIPE_B), FDI_RX_CTL(PIPE_C))
917 calc_index(offset, FDI_TX_CTL(PIPE_A), FDI_TX_CTL(PIPE_B), FDI_TX_CTL(PIPE_C))
920 calc_index(offset, FDI_RX_IMR(PIPE_A), FDI_RX_IMR(PIPE_B), FDI_RX_IMR(PIPE_C))
1028 calc_index(offset, DSPSURF(display, PIPE_A), DSPSURF(display, PIPE_B), DSPSURF(display, PIPE_C))
1052 calc_index(offset, SPRSURF(PIPE_A), SPRSURF(PIPE_B), SPRSURF(PIPE_C))
2311 MMIO_DH(DSPSURF(display, PIPE_B), D_ALL, NULL, pri_surf_mmio_write); in init_generic_mmio_info()
2312 MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL, in init_generic_mmio_info()
2320 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write); in init_generic_mmio_info()
2321 MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL, in init_generic_mmio_info()
2344 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write); in init_generic_mmio_info()
[all …]
H A Dreg.h70 (((p) == PIPE_B) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50088)) : \
79 (((reg) == 0x50088 || (reg) == 0x50098) ? (PIPE_B) : \
H A Ddisplay.c64 pipe = PIPE_B; in get_edp_pipe()
645 [PIPE_B] = PIPE_B_VBLANK, in emulate_vblank_on_pipe()
H A Dcmd_parser.c1298 [1] = {PIPE_B, PLANE_A, PRIMARY_B_FLIP_DONE}, in gen8_decode_mi_display_flip()
1300 [3] = {PIPE_B, PLANE_B, SPRITE_B_FLIP_DONE}, in gen8_decode_mi_display_flip()
1357 info->pipe = PIPE_B; in skl_decode_mi_display_flip()
1371 info->pipe = PIPE_B; in skl_decode_mi_display_flip()