Searched refs:PCS (Results 1 – 10 of 10) sorted by relevance
219 should be used to configure the MAC when the MAC and PCS are not249 10. Some Ethernet controllers work in pair with a PCS (Physical Coding Sublayer)252 PCS whose operation is transparent, some other require dedicated PCS254 provides a PCS abstraction through :c:type:`struct phylink_pcs <phylink_pcs>`.256 Identify if your driver has one or more internal PCS blocks, and/or if257 your controller can use an external PCS block that might be internally260 If your controller doesn't have any internal PCS, you can go to step 11.262 If your Ethernet controller contains one or several PCS blocks, create263 one :c:type:`struct phylink_pcs <phylink_pcs>` instance per PCS block within271 configure your PCS. Create a :c:func:`pcs_get_state` function that reports[all …]
54 | MC firmware polling MAC PCS for link |56 | | PCS | | PCS | | PCS | | PCS | |65 the MC firmware by polling the MAC PCS. Without the need to register a187 mode, the MC firmware does not access the PCS registers). One can check for
24 1GE and 2.5GE modes via the LynxI PCS, and 5GE and 10GE modes25 via the USXGMII PCS found in MediaTek SoCs with 10G Ethernet.
149 pub const PCS: Self = Mmd(uapi::MDIO_MMD_PCS as u8);147 pub const PCS: Self = Mmd(uapi::MDIO_MMD_PCS as u8); global() constant
331 __be64 PCS; member
310 stats->rx_errors = be64_to_cpu(mlx4_en_stats->PCS) + in mlx4_en_DUMP_ETH_STATS()
606 FM801 chip with a TEA5757 tuner (MediaForte SF256-PCS, SF256-PCP and
630 NSSCC receives the clock sources from GCC, CMN PLL and UNIPHY (PCS).
29 D: Synopsys DesignWare XPCS MDIO/PCS driver.
15602 LYNX PCS MODULE16628 MEDIATEK ETHERNET PCS DRIVER