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Searched refs:IS_CHERRYVIEW (Results 1 – 25 of 61) sorted by relevance

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/linux/drivers/gpu/drm/i915/display/
H A Dg4x_dp.c54 return IS_CHERRYVIEW(i915) ? &chv_dpll[0] : &vlv_dpll[0]; in vlv_get_dpll()
70 } else if (IS_CHERRYVIEW(dev_priv)) { in g4x_dp_set_clock()
161 if (IS_CHERRYVIEW(dev_priv)) in intel_dp_prepare()
296 else if (IS_CHERRYVIEW(dev_priv)) in g4x_dp_port_enabled()
480 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_dp_link_down()
696 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_enable_dp()
706 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_enable_dp()
709 if (IS_CHERRYVIEW(dev_priv)) in intel_enable_dp()
1276 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_dp_encoder_reset()
1345 if (IS_CHERRYVIEW(dev_priv)) { in g4x_dp_init()
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H A Dintel_pps.c33 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { in pps_name()
123 if (IS_CHERRYVIEW(dev_priv)) in vlv_power_sequencer_kick()
135 release_cl_override = IS_CHERRYVIEW(dev_priv) && in vlv_power_sequencer_kick()
357 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in intel_num_pps()
411 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { in pps_initial_setup()
503 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_pps_get_registers()
550 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in edp_have_panel_power()
564 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in edp_have_panel_vdd()
1558 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in pps_init_registers()
1616 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in intel_pps_encoder_reset()
[all …]
H A Di9xx_plane.c142 if (IS_CHERRYVIEW(dev_priv)) in i9xx_plane_has_windowing()
471 if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) { in i9xx_plane_update_arm()
875 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_primary_plane_create()
909 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_primary_plane_create()
932 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_primary_plane_create()
951 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_primary_plane_create()
993 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { in intel_primary_plane_create()
1097 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B && in i9xx_get_initial_plane_config()
H A Dintel_pipe_crc.c149 if (!IS_CHERRYVIEW(dev_priv)) in vlv_pipe_crc_ctl_reg()
410 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in get_new_crc_ctl_reg()
540 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_is_valid_crc_source()
616 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_crtc_set_crc_source()
H A Dintel_lpe_audio.c122 pdata->num_ports = IS_CHERRYVIEW(dev_priv) ? 3 : 2; /* B,C,D or B,C */ in lpe_audio_platdev_create()
187 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in lpe_audio_detect()
H A Dintel_vga.c19 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in intel_vga_cntrl_reg()
H A Dintel_sprite_uapi.c63 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in intel_sprite_set_colorkey_ioctl()
H A Dg4x_hdmi.c56 else if (IS_CHERRYVIEW(dev_priv)) in intel_hdmi_prepare()
740 if (IS_CHERRYVIEW(dev_priv)) { in g4x_hdmi_init()
767 if (IS_CHERRYVIEW(dev_priv)) { in g4x_hdmi_init()
H A Dintel_crtc_state_dump.c346 if (IS_CHERRYVIEW(i915)) in intel_crtc_state_dump()
368 else if (IS_CHERRYVIEW(i915)) in intel_crtc_state_dump()
H A Dintel_sprite.c420 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) in vlv_sprite_update_arm()
1385 if (IS_CHERRYVIEW(dev_priv) && in chv_plane_check_rotation()
1603 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_sprite_plane_create()
1613 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { in intel_sprite_plane_create()
1666 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { in intel_sprite_plane_create()
H A Dvlv_dsi_pll.c75 if (IS_CHERRYVIEW(dev_priv)) { in dsi_calc_mnp()
125 int refclk = IS_CHERRYVIEW(dev_priv) ? 100000 : 25000; in vlv_dsi_pclk()
H A Dintel_hotplug_irq.c140 IS_CHERRYVIEW(dev_priv)) in intel_hpd_init_pins()
422 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in i9xx_hpd_irq_ack()
464 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in i9xx_hpd_irq_handler()
479 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in i9xx_hpd_irq_handler()
H A Dintel_cdclk.c592 if (IS_CHERRYVIEW(dev_priv)) in vlv_program_pfi_credits()
599 if (IS_CHERRYVIEW(dev_priv)) in vlv_program_pfi_credits()
2701 else if (IS_CHERRYVIEW(dev_priv)) in intel_pixel_rate_to_cdclk()
2812 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in intel_crtc_compute_min_cdclk()
3385 else if (IS_CHERRYVIEW(dev_priv)) in intel_compute_max_dotclk()
3454 } else if (IS_CHERRYVIEW(dev_priv)) { in intel_update_max_cdclk()
3488 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_update_cdclk()
3576 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_read_rawclk()
3798 } else if (IS_CHERRYVIEW(dev_priv)) { in intel_init_cdclk_hooks()
H A Dintel_display.c187 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) in intel_update_czclk()
2129 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { in valleyview_crtc_enable()
2141 if (IS_CHERRYVIEW(dev_priv)) in valleyview_crtc_enable()
2250 if (IS_CHERRYVIEW(dev_priv)) in i9xx_crtc_disable()
2651 return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv); in intel_cpu_transcoder_has_m2_n2()
2940 IS_CHERRYVIEW(dev_priv)) { in i9xx_set_pipeconf()
2973 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in i9xx_set_pipeconf()
3073 IS_CHERRYVIEW(dev_priv)) { in i9xx_get_pipe_config()
3090 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in i9xx_get_pipe_config()
3098 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in i9xx_get_pipe_config()
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H A Dintel_dpll.c398 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) in i9xx_dpll_get_hw_state()
409 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { in i9xx_dpll_get_hw_state()
826 if (IS_CHERRYVIEW(to_i915(dev))) { in vlv_PLL_is_optimal()
1802 else if (IS_CHERRYVIEW(dev_priv)) in intel_dpll_init_clock_hook()
2227 if (IS_CHERRYVIEW(dev_priv)) { in vlv_force_pll_on()
2311 if (IS_CHERRYVIEW(dev_priv)) in vlv_force_pll_off()
/linux/drivers/gpu/drm/i915/selftests/
H A Dintel_uncore.c174 if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915)) { in live_forcewake_ops()
286 !IS_CHERRYVIEW(gt->i915)) in live_forcewake_domains()
/linux/drivers/gpu/drm/i915/gt/
H A Dintel_gtt.c38 return IS_CHERRYVIEW(i915) || intel_ggtt_update_needs_vtd_wa(i915); in intel_vm_no_concurrent_access_wa()
450 else if (IS_CHERRYVIEW(i915)) in gtt_write_workarounds()
689 else if (IS_CHERRYVIEW(i915) || IS_GEN9_LP(i915)) in setup_private_pat()
H A Dintel_rc6.c616 if (IS_CHERRYVIEW(i915)) in intel_rc6_init()
654 if (IS_CHERRYVIEW(i915)) in intel_rc6_enable()
814 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { in intel_rc6_residency_ns()
H A Dintel_rps.c843 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in rps_set()
1545 else if (IS_CHERRYVIEW(i915)) in intel_rps_enable()
1645 else if (IS_CHERRYVIEW(i915)) in intel_gpu_freq()
1662 else if (IS_CHERRYVIEW(i915)) in intel_freq_opcode()
1849 adj = IS_CHERRYVIEW(gt->i915) ? 2 : 1; in rps_work()
1865 adj = IS_CHERRYVIEW(gt->i915) ? -2 : -1; in rps_work()
1993 if (IS_CHERRYVIEW(i915)) in intel_rps_init()
2082 else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in intel_rps_get_cagf()
2111 } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { in __read_cagf()
H A Dselftest_rc6.c51 if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915)) in live_rc6_manual()
H A Dintel_gt_pm_debugfs.c327 else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in drpc_show()
358 } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { in intel_gt_pm_frequency_dump()
/linux/drivers/gpu/drm/xe/compat-i915-headers/
H A Di915_drv.h47 #define IS_CHERRYVIEW(dev_priv) (dev_priv && 0) macro
/linux/drivers/gpu/drm/i915/
H A Dvlv_suspend.c386 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) in vlv_suspend_complete()
431 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) in vlv_resume_prepare()
H A Dvlv_sideband.c206 if (IS_CHERRYVIEW(i915)) in vlv_dpio_phy_iosf_port()
/linux/drivers/gpu/drm/i915/soc/
H A Dintel_gmch.c89 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in intel_gmch_bar_setup()

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