1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2013-2021 Intel Corporation
4 */
5
6 #include "i915_drv.h"
7 #include "i915_iosf_mbi.h"
8 #include "i915_reg.h"
9 #include "vlv_sideband.h"
10
11 #include "display/intel_dpio_phy.h"
12
13 /*
14 * IOSF sideband, see VLV2_SidebandMsg_HAS.docx and
15 * VLV_VLV2_PUNIT_HAS_0.8.docx
16 */
17
18 /* Standard MMIO read, non-posted */
19 #define SB_MRD_NP 0x00
20 /* Standard MMIO write, non-posted */
21 #define SB_MWR_NP 0x01
22 /* Private register read, double-word addressing, non-posted */
23 #define SB_CRRDDA_NP 0x06
24 /* Private register write, double-word addressing, non-posted */
25 #define SB_CRWRDA_NP 0x07
26
ping(void * info)27 static void ping(void *info)
28 {
29 }
30
__vlv_punit_get(struct drm_i915_private * i915)31 static void __vlv_punit_get(struct drm_i915_private *i915)
32 {
33 iosf_mbi_punit_acquire();
34
35 /*
36 * Prevent the cpu from sleeping while we use this sideband, otherwise
37 * the punit may cause a machine hang. The issue appears to be isolated
38 * with changing the power state of the CPU package while changing
39 * the power state via the punit, and we have only observed it
40 * reliably on 4-core Baytail systems suggesting the issue is in the
41 * power delivery mechanism and likely to be board/function
42 * specific. Hence we presume the workaround needs only be applied
43 * to the Valleyview P-unit and not all sideband communications.
44 */
45 if (IS_VALLEYVIEW(i915)) {
46 cpu_latency_qos_update_request(&i915->sb_qos, 0);
47 on_each_cpu(ping, NULL, 1);
48 }
49 }
50
__vlv_punit_put(struct drm_i915_private * i915)51 static void __vlv_punit_put(struct drm_i915_private *i915)
52 {
53 if (IS_VALLEYVIEW(i915))
54 cpu_latency_qos_update_request(&i915->sb_qos,
55 PM_QOS_DEFAULT_VALUE);
56
57 iosf_mbi_punit_release();
58 }
59
vlv_iosf_sb_get(struct drm_i915_private * i915,unsigned long ports)60 void vlv_iosf_sb_get(struct drm_i915_private *i915, unsigned long ports)
61 {
62 if (ports & BIT(VLV_IOSF_SB_PUNIT))
63 __vlv_punit_get(i915);
64
65 mutex_lock(&i915->sb_lock);
66 }
67
vlv_iosf_sb_put(struct drm_i915_private * i915,unsigned long ports)68 void vlv_iosf_sb_put(struct drm_i915_private *i915, unsigned long ports)
69 {
70 mutex_unlock(&i915->sb_lock);
71
72 if (ports & BIT(VLV_IOSF_SB_PUNIT))
73 __vlv_punit_put(i915);
74 }
75
vlv_sideband_rw(struct drm_i915_private * i915,u32 devfn,u32 port,u32 opcode,u32 addr,u32 * val)76 static int vlv_sideband_rw(struct drm_i915_private *i915,
77 u32 devfn, u32 port, u32 opcode,
78 u32 addr, u32 *val)
79 {
80 struct intel_uncore *uncore = &i915->uncore;
81 const bool is_read = (opcode == SB_MRD_NP || opcode == SB_CRRDDA_NP);
82 int err;
83
84 lockdep_assert_held(&i915->sb_lock);
85 if (port == IOSF_PORT_PUNIT)
86 iosf_mbi_assert_punit_acquired();
87
88 /* Flush the previous comms, just in case it failed last time. */
89 if (intel_wait_for_register(uncore,
90 VLV_IOSF_DOORBELL_REQ, IOSF_SB_BUSY, 0,
91 5)) {
92 drm_dbg(&i915->drm, "IOSF sideband idle wait (%s) timed out\n",
93 is_read ? "read" : "write");
94 return -EAGAIN;
95 }
96
97 preempt_disable();
98
99 intel_uncore_write_fw(uncore, VLV_IOSF_ADDR, addr);
100 intel_uncore_write_fw(uncore, VLV_IOSF_DATA, is_read ? 0 : *val);
101 intel_uncore_write_fw(uncore, VLV_IOSF_DOORBELL_REQ,
102 (devfn << IOSF_DEVFN_SHIFT) |
103 (opcode << IOSF_OPCODE_SHIFT) |
104 (port << IOSF_PORT_SHIFT) |
105 (0xf << IOSF_BYTE_ENABLES_SHIFT) |
106 (0 << IOSF_BAR_SHIFT) |
107 IOSF_SB_BUSY);
108
109 if (__intel_wait_for_register_fw(uncore,
110 VLV_IOSF_DOORBELL_REQ, IOSF_SB_BUSY, 0,
111 10000, 0, NULL) == 0) {
112 if (is_read)
113 *val = intel_uncore_read_fw(uncore, VLV_IOSF_DATA);
114 err = 0;
115 } else {
116 drm_dbg(&i915->drm, "IOSF sideband finish wait (%s) timed out\n",
117 is_read ? "read" : "write");
118 err = -ETIMEDOUT;
119 }
120
121 preempt_enable();
122
123 return err;
124 }
125
vlv_punit_read(struct drm_i915_private * i915,u32 addr)126 u32 vlv_punit_read(struct drm_i915_private *i915, u32 addr)
127 {
128 u32 val = 0;
129
130 vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
131 SB_CRRDDA_NP, addr, &val);
132
133 return val;
134 }
135
vlv_punit_write(struct drm_i915_private * i915,u32 addr,u32 val)136 int vlv_punit_write(struct drm_i915_private *i915, u32 addr, u32 val)
137 {
138 return vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
139 SB_CRWRDA_NP, addr, &val);
140 }
141
vlv_bunit_read(struct drm_i915_private * i915,u32 reg)142 u32 vlv_bunit_read(struct drm_i915_private *i915, u32 reg)
143 {
144 u32 val = 0;
145
146 vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_BUNIT,
147 SB_CRRDDA_NP, reg, &val);
148
149 return val;
150 }
151
vlv_bunit_write(struct drm_i915_private * i915,u32 reg,u32 val)152 void vlv_bunit_write(struct drm_i915_private *i915, u32 reg, u32 val)
153 {
154 vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_BUNIT,
155 SB_CRWRDA_NP, reg, &val);
156 }
157
vlv_nc_read(struct drm_i915_private * i915,u8 addr)158 u32 vlv_nc_read(struct drm_i915_private *i915, u8 addr)
159 {
160 u32 val = 0;
161
162 vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_NC,
163 SB_CRRDDA_NP, addr, &val);
164
165 return val;
166 }
167
vlv_cck_read(struct drm_i915_private * i915,u32 reg)168 u32 vlv_cck_read(struct drm_i915_private *i915, u32 reg)
169 {
170 u32 val = 0;
171
172 vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_CCK,
173 SB_CRRDDA_NP, reg, &val);
174
175 return val;
176 }
177
vlv_cck_write(struct drm_i915_private * i915,u32 reg,u32 val)178 void vlv_cck_write(struct drm_i915_private *i915, u32 reg, u32 val)
179 {
180 vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_CCK,
181 SB_CRWRDA_NP, reg, &val);
182 }
183
vlv_ccu_read(struct drm_i915_private * i915,u32 reg)184 u32 vlv_ccu_read(struct drm_i915_private *i915, u32 reg)
185 {
186 u32 val = 0;
187
188 vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_CCU,
189 SB_CRRDDA_NP, reg, &val);
190
191 return val;
192 }
193
vlv_ccu_write(struct drm_i915_private * i915,u32 reg,u32 val)194 void vlv_ccu_write(struct drm_i915_private *i915, u32 reg, u32 val)
195 {
196 vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_CCU,
197 SB_CRWRDA_NP, reg, &val);
198 }
199
vlv_dpio_phy_iosf_port(struct drm_i915_private * i915,enum dpio_phy phy)200 static u32 vlv_dpio_phy_iosf_port(struct drm_i915_private *i915, enum dpio_phy phy)
201 {
202 /*
203 * IOSF_PORT_DPIO: VLV x2 PHY (DP/HDMI B and C), CHV x1 PHY (DP/HDMI D)
204 * IOSF_PORT_DPIO_2: CHV x2 PHY (DP/HDMI B and C)
205 */
206 if (IS_CHERRYVIEW(i915))
207 return phy == DPIO_PHY0 ? IOSF_PORT_DPIO_2 : IOSF_PORT_DPIO;
208 else
209 return IOSF_PORT_DPIO;
210 }
211
vlv_dpio_read(struct drm_i915_private * i915,enum dpio_phy phy,int reg)212 u32 vlv_dpio_read(struct drm_i915_private *i915, enum dpio_phy phy, int reg)
213 {
214 u32 port = vlv_dpio_phy_iosf_port(i915, phy);
215 u32 val = 0;
216
217 vlv_sideband_rw(i915, DPIO_DEVFN, port, SB_MRD_NP, reg, &val);
218
219 /*
220 * FIXME: There might be some registers where all 1's is a valid value,
221 * so ideally we should check the register offset instead...
222 */
223 drm_WARN(&i915->drm, val == 0xffffffff,
224 "DPIO PHY%d read reg 0x%x == 0x%x\n",
225 phy, reg, val);
226
227 return val;
228 }
229
vlv_dpio_write(struct drm_i915_private * i915,enum dpio_phy phy,int reg,u32 val)230 void vlv_dpio_write(struct drm_i915_private *i915,
231 enum dpio_phy phy, int reg, u32 val)
232 {
233 u32 port = vlv_dpio_phy_iosf_port(i915, phy);
234
235 vlv_sideband_rw(i915, DPIO_DEVFN, port, SB_MWR_NP, reg, &val);
236 }
237
vlv_flisdsi_read(struct drm_i915_private * i915,u32 reg)238 u32 vlv_flisdsi_read(struct drm_i915_private *i915, u32 reg)
239 {
240 u32 val = 0;
241
242 vlv_sideband_rw(i915, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRRDDA_NP,
243 reg, &val);
244 return val;
245 }
246
vlv_flisdsi_write(struct drm_i915_private * i915,u32 reg,u32 val)247 void vlv_flisdsi_write(struct drm_i915_private *i915, u32 reg, u32 val)
248 {
249 vlv_sideband_rw(i915, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRWRDA_NP,
250 reg, &val);
251 }
252