1a13144e2SJani Nikula // SPDX-License-Identifier: MIT
2a13144e2SJani Nikula /*
3a13144e2SJani Nikula * Copyright © 2023 Intel Corporation
4a13144e2SJani Nikula */
5a13144e2SJani Nikula
6a13144e2SJani Nikula #include <linux/pci.h>
7a13144e2SJani Nikula #include <linux/pnp.h>
85846cdfdSUma Shankar #include <linux/vgaarb.h>
9a13144e2SJani Nikula
10a13144e2SJani Nikula #include <drm/drm_managed.h>
11*03c7918dSJani Nikula #include <drm/intel/i915_drm.h>
12a13144e2SJani Nikula
13a13144e2SJani Nikula #include "i915_drv.h"
14a13144e2SJani Nikula #include "intel_gmch.h"
15a13144e2SJani Nikula #include "intel_pci_config.h"
16a13144e2SJani Nikula
intel_gmch_bridge_release(struct drm_device * dev,void * bridge)17a13144e2SJani Nikula static void intel_gmch_bridge_release(struct drm_device *dev, void *bridge)
18a13144e2SJani Nikula {
19a13144e2SJani Nikula pci_dev_put(bridge);
20a13144e2SJani Nikula }
21a13144e2SJani Nikula
intel_gmch_bridge_setup(struct drm_i915_private * i915)22b1e7d8b0SJani Nikula int intel_gmch_bridge_setup(struct drm_i915_private *i915)
23a13144e2SJani Nikula {
24b1e7d8b0SJani Nikula int domain = pci_domain_nr(to_pci_dev(i915->drm.dev)->bus);
25a13144e2SJani Nikula
26b1e7d8b0SJani Nikula i915->gmch.pdev = pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
27b1e7d8b0SJani Nikula if (!i915->gmch.pdev) {
28b1e7d8b0SJani Nikula drm_err(&i915->drm, "bridge device not found\n");
29a13144e2SJani Nikula return -EIO;
30a13144e2SJani Nikula }
31a13144e2SJani Nikula
32b1e7d8b0SJani Nikula return drmm_add_action_or_reset(&i915->drm, intel_gmch_bridge_release,
33b1e7d8b0SJani Nikula i915->gmch.pdev);
34a13144e2SJani Nikula }
35a13144e2SJani Nikula
mchbar_reg(struct drm_i915_private * i915)36e5aaad61SVille Syrjälä static int mchbar_reg(struct drm_i915_private *i915)
37e5aaad61SVille Syrjälä {
38e5aaad61SVille Syrjälä return GRAPHICS_VER(i915) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
39e5aaad61SVille Syrjälä }
40e5aaad61SVille Syrjälä
41a13144e2SJani Nikula /* Allocate space for the MCH regs if needed, return nonzero on error */
42a13144e2SJani Nikula static int
intel_alloc_mchbar_resource(struct drm_i915_private * i915)43b1e7d8b0SJani Nikula intel_alloc_mchbar_resource(struct drm_i915_private *i915)
44a13144e2SJani Nikula {
45a13144e2SJani Nikula u32 temp_lo, temp_hi = 0;
46a13144e2SJani Nikula u64 mchbar_addr;
47a13144e2SJani Nikula int ret;
48a13144e2SJani Nikula
49b1e7d8b0SJani Nikula if (GRAPHICS_VER(i915) >= 4)
50e5aaad61SVille Syrjälä pci_read_config_dword(i915->gmch.pdev, mchbar_reg(i915) + 4, &temp_hi);
51e5aaad61SVille Syrjälä pci_read_config_dword(i915->gmch.pdev, mchbar_reg(i915), &temp_lo);
52a13144e2SJani Nikula mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
53a13144e2SJani Nikula
54a13144e2SJani Nikula /* If ACPI doesn't have it, assume we need to allocate it ourselves */
55b02a9a0cSArnd Bergmann if (IS_ENABLED(CONFIG_PNP) && mchbar_addr &&
56a13144e2SJani Nikula pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
57a13144e2SJani Nikula return 0;
58a13144e2SJani Nikula
59a13144e2SJani Nikula /* Get some space for it */
60b1e7d8b0SJani Nikula i915->gmch.mch_res.name = "i915 MCHBAR";
61b1e7d8b0SJani Nikula i915->gmch.mch_res.flags = IORESOURCE_MEM;
62b1e7d8b0SJani Nikula ret = pci_bus_alloc_resource(i915->gmch.pdev->bus,
63b1e7d8b0SJani Nikula &i915->gmch.mch_res,
64a13144e2SJani Nikula MCHBAR_SIZE, MCHBAR_SIZE,
65a13144e2SJani Nikula PCIBIOS_MIN_MEM,
66a13144e2SJani Nikula 0, pcibios_align_resource,
67b1e7d8b0SJani Nikula i915->gmch.pdev);
68a13144e2SJani Nikula if (ret) {
69b1e7d8b0SJani Nikula drm_dbg(&i915->drm, "failed bus alloc: %d\n", ret);
70b1e7d8b0SJani Nikula i915->gmch.mch_res.start = 0;
71a13144e2SJani Nikula return ret;
72a13144e2SJani Nikula }
73a13144e2SJani Nikula
74b1e7d8b0SJani Nikula if (GRAPHICS_VER(i915) >= 4)
75e5aaad61SVille Syrjälä pci_write_config_dword(i915->gmch.pdev, mchbar_reg(i915) + 4,
76b1e7d8b0SJani Nikula upper_32_bits(i915->gmch.mch_res.start));
77a13144e2SJani Nikula
78e5aaad61SVille Syrjälä pci_write_config_dword(i915->gmch.pdev, mchbar_reg(i915),
79b1e7d8b0SJani Nikula lower_32_bits(i915->gmch.mch_res.start));
80a13144e2SJani Nikula return 0;
81a13144e2SJani Nikula }
82a13144e2SJani Nikula
83a13144e2SJani Nikula /* Setup MCHBAR if possible, return true if we should disable it again */
intel_gmch_bar_setup(struct drm_i915_private * i915)84b1e7d8b0SJani Nikula void intel_gmch_bar_setup(struct drm_i915_private *i915)
85a13144e2SJani Nikula {
86a13144e2SJani Nikula u32 temp;
87a13144e2SJani Nikula bool enabled;
88a13144e2SJani Nikula
89b1e7d8b0SJani Nikula if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
90a13144e2SJani Nikula return;
91a13144e2SJani Nikula
92b1e7d8b0SJani Nikula i915->gmch.mchbar_need_disable = false;
93a13144e2SJani Nikula
94b1e7d8b0SJani Nikula if (IS_I915G(i915) || IS_I915GM(i915)) {
95b1e7d8b0SJani Nikula pci_read_config_dword(i915->gmch.pdev, DEVEN, &temp);
96a13144e2SJani Nikula enabled = !!(temp & DEVEN_MCHBAR_EN);
97a13144e2SJani Nikula } else {
98e5aaad61SVille Syrjälä pci_read_config_dword(i915->gmch.pdev, mchbar_reg(i915), &temp);
99a13144e2SJani Nikula enabled = temp & 1;
100a13144e2SJani Nikula }
101a13144e2SJani Nikula
102a13144e2SJani Nikula /* If it's already enabled, don't have to do anything */
103a13144e2SJani Nikula if (enabled)
104a13144e2SJani Nikula return;
105a13144e2SJani Nikula
106b1e7d8b0SJani Nikula if (intel_alloc_mchbar_resource(i915))
107a13144e2SJani Nikula return;
108a13144e2SJani Nikula
109b1e7d8b0SJani Nikula i915->gmch.mchbar_need_disable = true;
110a13144e2SJani Nikula
111a13144e2SJani Nikula /* Space is allocated or reserved, so enable it. */
112b1e7d8b0SJani Nikula if (IS_I915G(i915) || IS_I915GM(i915)) {
113b1e7d8b0SJani Nikula pci_write_config_dword(i915->gmch.pdev, DEVEN,
114a13144e2SJani Nikula temp | DEVEN_MCHBAR_EN);
115a13144e2SJani Nikula } else {
116e5aaad61SVille Syrjälä pci_read_config_dword(i915->gmch.pdev, mchbar_reg(i915), &temp);
117e5aaad61SVille Syrjälä pci_write_config_dword(i915->gmch.pdev, mchbar_reg(i915), temp | 1);
118a13144e2SJani Nikula }
119a13144e2SJani Nikula }
120a13144e2SJani Nikula
intel_gmch_bar_teardown(struct drm_i915_private * i915)121b1e7d8b0SJani Nikula void intel_gmch_bar_teardown(struct drm_i915_private *i915)
122a13144e2SJani Nikula {
123b1e7d8b0SJani Nikula if (i915->gmch.mchbar_need_disable) {
124b1e7d8b0SJani Nikula if (IS_I915G(i915) || IS_I915GM(i915)) {
125a13144e2SJani Nikula u32 deven_val;
126a13144e2SJani Nikula
127b1e7d8b0SJani Nikula pci_read_config_dword(i915->gmch.pdev, DEVEN,
128a13144e2SJani Nikula &deven_val);
129a13144e2SJani Nikula deven_val &= ~DEVEN_MCHBAR_EN;
130b1e7d8b0SJani Nikula pci_write_config_dword(i915->gmch.pdev, DEVEN,
131a13144e2SJani Nikula deven_val);
132a13144e2SJani Nikula } else {
133a13144e2SJani Nikula u32 mchbar_val;
134a13144e2SJani Nikula
135e5aaad61SVille Syrjälä pci_read_config_dword(i915->gmch.pdev, mchbar_reg(i915),
136a13144e2SJani Nikula &mchbar_val);
137a13144e2SJani Nikula mchbar_val &= ~1;
138e5aaad61SVille Syrjälä pci_write_config_dword(i915->gmch.pdev, mchbar_reg(i915),
139a13144e2SJani Nikula mchbar_val);
140a13144e2SJani Nikula }
141a13144e2SJani Nikula }
142a13144e2SJani Nikula
143b1e7d8b0SJani Nikula if (i915->gmch.mch_res.start)
144b1e7d8b0SJani Nikula release_resource(&i915->gmch.mch_res);
145a13144e2SJani Nikula }
146eee838e4SJani Nikula
intel_gmch_vga_set_state(struct drm_i915_private * i915,bool enable_decode)147eee838e4SJani Nikula int intel_gmch_vga_set_state(struct drm_i915_private *i915, bool enable_decode)
148eee838e4SJani Nikula {
149eee838e4SJani Nikula unsigned int reg = DISPLAY_VER(i915) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
150eee838e4SJani Nikula u16 gmch_ctrl;
151eee838e4SJani Nikula
152eee838e4SJani Nikula if (pci_read_config_word(i915->gmch.pdev, reg, &gmch_ctrl)) {
153eee838e4SJani Nikula drm_err(&i915->drm, "failed to read control word\n");
154eee838e4SJani Nikula return -EIO;
155eee838e4SJani Nikula }
156eee838e4SJani Nikula
157eee838e4SJani Nikula if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !enable_decode)
158eee838e4SJani Nikula return 0;
159eee838e4SJani Nikula
160eee838e4SJani Nikula if (enable_decode)
161eee838e4SJani Nikula gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
162eee838e4SJani Nikula else
163eee838e4SJani Nikula gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
164eee838e4SJani Nikula
165eee838e4SJani Nikula if (pci_write_config_word(i915->gmch.pdev, reg, gmch_ctrl)) {
166eee838e4SJani Nikula drm_err(&i915->drm, "failed to write control word\n");
167eee838e4SJani Nikula return -EIO;
168eee838e4SJani Nikula }
169eee838e4SJani Nikula
170eee838e4SJani Nikula return 0;
171eee838e4SJani Nikula }
1725846cdfdSUma Shankar
intel_gmch_vga_set_decode(struct pci_dev * pdev,bool enable_decode)1735846cdfdSUma Shankar unsigned int intel_gmch_vga_set_decode(struct pci_dev *pdev, bool enable_decode)
1745846cdfdSUma Shankar {
1755846cdfdSUma Shankar struct drm_i915_private *i915 = pdev_to_i915(pdev);
1765846cdfdSUma Shankar
1775846cdfdSUma Shankar intel_gmch_vga_set_state(i915, enable_decode);
1785846cdfdSUma Shankar
1795846cdfdSUma Shankar if (enable_decode)
1805846cdfdSUma Shankar return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1815846cdfdSUma Shankar VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1825846cdfdSUma Shankar else
1835846cdfdSUma Shankar return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1845846cdfdSUma Shankar }
185