Lines Matching refs:IS_CHERRYVIEW
187 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) in intel_update_czclk()
2129 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { in valleyview_crtc_enable()
2141 if (IS_CHERRYVIEW(dev_priv)) in valleyview_crtc_enable()
2250 if (IS_CHERRYVIEW(dev_priv)) in i9xx_crtc_disable()
2651 return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv); in intel_cpu_transcoder_has_m2_n2()
2940 IS_CHERRYVIEW(dev_priv)) { in i9xx_set_pipeconf()
2973 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in i9xx_set_pipeconf()
3073 IS_CHERRYVIEW(dev_priv)) { in i9xx_get_pipe_config()
3090 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in i9xx_get_pipe_config()
3098 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in i9xx_get_pipe_config()
3132 if (IS_CHERRYVIEW(dev_priv)) in i9xx_get_pipe_config()
4395 IS_CHERRYVIEW(dev_priv))) in compute_baseline_pipe_bpp()
4635 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_crtc_prepare_cleared_state()
5329 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_pipe_config_compare()
5365 if (IS_CHERRYVIEW(dev_priv)) in intel_pipe_config_compare()
5838 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) || in active_planes_affects_min_cdclk()
7845 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_setup_outputs()
7880 if (IS_CHERRYVIEW(dev_priv)) { in intel_setup_outputs()
8179 } else if (IS_CHERRYVIEW(dev_priv) || in intel_init_display_hooks()