| /linux/Documentation/driver-api/media/drivers/ |
| H A D | pxa_camera.rst | 13 This is due to DMA constraints, which transfers only planes of 8 byte
26 capture. The new buffers are "appended" at the tail of the DMA chain, and
46 | | DMA: stop | | DMA: stop | |
53 | | DMA hotlink missed | | Capture running | |
56 | | DMA: stop | / | DMA: run | | |
58 | ^ /DMA still | | channels |
59 | | capture list / running | DMA Irq End | not |
66 | DMA: run | | DMA: run | |
75 | DMA: run | | DMA: stop |
84 - "DMA: stop" means all 3 DMA channels are stopped
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| /linux/Documentation/devicetree/bindings/powerpc/fsl/ |
| H A D | dma.txt | 1 * Freescale DMA Controllers
3 ** Freescale Elo DMA Controller
4 This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
10 - reg : DMA General Status Register, i.e. DGSR which contains
11 status for all the 4 DMA channels
13 DMA channels and the address space of the DMA controller
15 - interrupts : interrupt specifier for DMA IRQ
17 - DMA channel nodes:
20 - reg : DMA channel specific registers
21 - cell-index : DMA channel index starts at 0.
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| /linux/Documentation/arch/arm/stm32/ |
| H A D | stm32-dma-mdma-chaining.rst | 4 STM32 DMA-MDMA chaining
11 This document describes the STM32 DMA-MDMA chaining feature. But before going
15 direct memory access controllers (DMA).
17 STM32MP1 SoCs embed both STM32 DMA and STM32 MDMA controllers. STM32 DMA
18 request routing capabilities are enhanced by a DMA request multiplexer
23 STM32 DMAMUX routes any DMA request from a given peripheral to any STM32 DMA
24 controller (STM32MP1 counts two STM32 DMA controllers) channels.
26 **STM32 DMA**
28 STM32 DMA is mainly used to implement central data buffer storage (usually in
35 STM32 MDMA (Master DMA) is mainly used to manage direct data transfers between
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| /linux/Documentation/core-api/ |
| H A D | dma-isa-lpc.rst | 2 DMA with ISA and LPC devices
7 This document describes how to do DMA transfers using the old ISA DMA
9 uses the same DMA system so it will be around for quite some time.
14 To do ISA style DMA you need to include two headers::
19 The first is the generic DMA API used to convert virtual addresses to
22 The second contains the routines specific to ISA DMA transfers. Since
30 The ISA DMA controller has some very strict requirements on which
34 (You usually need a special buffer for DMA transfers instead of
37 The DMA-able address space is the lowest 16 MB of _physical_ memory.
44 Unfortunately the memory available for ISA DMA is scarce so unless you
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| H A D | dma-api-howto.rst | 2 Dynamic DMA mapping Guide
9 This is a guide to device driver writers on how to use the DMA API
13 CPU and DMA addresses
16 There are several kinds of addresses involved in the DMA API, and it's
31 registers at an MMIO address, or if it performs DMA to read or write system
37 From a device's point of view, DMA uses the bus address space, but it may
40 so devices only need to use 32-bit DMA addresses.
75 If the device supports DMA, the driver sets up a buffer using kmalloc() or
79 cannot because DMA doesn't go through the CPU virtual memory system.
81 In some simple systems, the device can do DMA directly to physical address
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| /linux/Documentation/devicetree/bindings/soc/ti/ |
| H A D | keystone-navigator-dma.txt | 1 Keystone Navigator DMA Controller
4 on keystone devices. The Keystone Navigator DMA driver sets up the dma
9 an internal packet DMA module which is used as an infrastructure DMA
12 Navigator DMA cloud layout:
17 |-> DMA instance #0
19 |-> DMA instance #1
23 |-> DMA instance #n
25 Navigator DMA properties:
34 into DMA and the DMA uses it as the physical addresses to reach queue
36 they are relevant only from DMA perspective. The QMSS may not choose to
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| /linux/Documentation/devicetree/bindings/dma/ |
| H A D | ti-dma-crossbar.txt | 1 Texas Instruments DMA Crossbar (DMA request router)
4 - compatible: "ti,dra7-dma-crossbar" for DRA7xx DMA crossbar
7 - #dma-cells: Should be set to match with the DMA controller's dma-cells
9 - dma-requests: Number of DMA requests the crossbar can receive
10 - dma-masters: phandle pointing to the DMA controller
12 The DMA controller node need to have the following poroperties:
13 - dma-requests: Number of DMA requests the controller can handle
17 - ti,reserved-dma-request-ranges: DMA request ranges which should not be used
18 when mapping xbar input to DMA request, they are either
23 When requesting channel via ti,dra7-dma-crossbar, the DMA client must request
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| H A D | mpc512x-dma.txt | 1 * Freescale MPC512x and MPC8308 DMA Controller
3 The DMA controller in Freescale MPC512x and MPC8308 SoCs can move
7 Refer to "Generic DMA Controller and DMA request bindings" in
12 - reg: should contain the DMA controller registers location and length;
13 - interrupt for the DMA controller: syntax of interrupt client node
15 - #dma-cells: the length of the DMA specifier, must be <1>.
16 Each channel of this DMA controller has a peripheral request line,
29 DMA clients must use the format described in dma/dma.txt file.
|
| H A D | apm-xgene-dma.txt | 1 Applied Micro X-Gene SoC DMA nodes
3 DMA nodes are defined to describe on-chip DMA interfaces in
6 Required properties for DMA interfaces:
11 1st - DMA control and status register address space.
15 - interrupts: DMA has 5 interrupts sources. 1st interrupt is
16 DMA error reporting interrupt. 2nd, 3rd, 4th and 5th interrupts
17 are completion interrupts for each DMA channels.
|
| H A D | atmel-dma.txt | 1 * Atmel Direct Memory Access Controller (DMA)
5 - reg: Should contain DMA registers location and length.
6 - interrupts: Should contain DMA interrupt.
19 DMA clients connected to the Atmel DMA controller must use the format
24 1. A phandle pointing to the DMA controller.
27 3. Parameters for the at91 DMA configuration register which are device
|
| H A D | adi,axi-dmac.txt | |
| /linux/Documentation/driver-api/dmaengine/ |
| H A D | client.rst | 2 DMA Engine API Guide
7 .. note:: For DMA Engine usage in async_tx please see:
11 Below is a guide to device driver writers on how to use the Slave-DMA API of the
12 DMA Engine. This is applicable only for slave DMA usage only.
14 DMA usage
17 The slave DMA usage consists of following steps:
19 - Allocate a DMA slave channel
31 1. Allocate a DMA slave channel
33 Channel allocation is slightly different in the slave DMA context,
34 client drivers typically need a channel from a particular DMA
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| H A D | index.rst | 22 This book is a guide to device driver writers on how to use the Slave-DMA
23 API of the DMAEngine. This is applicable only for slave DMA usage only.
30 DMA Test documentation
33 This book introduces how to test DMA drivers using dmatest module.
40 PXA DMA documentation
43 This book adds some notes about PXA DMA
|
| /linux/Documentation/misc-devices/ |
| H A D | mrvl_cn10k_dpi.rst | 4 Marvell CN10K DMA packet interface (DPI) driver
10 DPI is a DMA packet interface hardware block in Marvell's CN10K silicon.
12 mailbox logic, and a set of DMA engines & DMA command queues.
15 requests from its VF functions and provisions DMA engine resources to
20 the DMA engines and VF device's DMA command queues. Also, driver creates
21 /dev/mrvl-cn10k-dpi node to set DMA engine and PEM (PCIe interface) port
26 DMA operations. Only VF devices are provisioned with DMA capabilities.
38 a pem port to which DMA engines are wired.
42 ioctl that sets DMA engine's fifo sizes & max outstanding load request
|
| /linux/Documentation/driver-api/ |
| H A D | dma-buf.rst | 5 hardware (DMA) access across multiple device drivers and subsystems, and
33 Shared DMA Buffers
39 Any device driver which wishes to be a part of DMA buffer sharing, can do so as
71 Mostly a DMA buffer file descriptor is simply an opaque object for userspace,
101 - Memory mapping the contents of the DMA buffer is also supported. See the
102 discussion below on `CPU Access to DMA Buffer Objects`_ for the full details.
104 - The DMA buffer FD is also pollable, see `Implicit Fence Poll Support`_ below for
107 - The DMA buffer FD also supports a few dma-buf-specific ioctls, see
108 `DMA Buffer ioctls`_ below for details.
110 Basic Operation and Device DMA Access
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| /linux/drivers/dma/stm32/ |
| H A D | Kconfig | 3 # STM32 DMA controllers drivers
8 bool "STMicroelectronics STM32 DMA support"
12 Enable support for the on-chip DMA controller on STMicroelectronics
14 If you have a board based on STM32 SoC with such DMA controller
15 and want to use DMA say Y here.
18 bool "STMicroelectronics STM32 DMA multiplexer support"
21 Enable support for the on-chip DMA multiplexer on STMicroelectronics
23 If you have a board based on STM32 SoC with such DMA multiplexer
27 bool "STMicroelectronics STM32 master DMA support"
34 If you have a board based on STM32 SoC with such DMA controller
|
| /linux/Documentation/driver-api/usb/ |
| H A D | dma.rst | 1 USB DMA
5 over how DMA may be used to perform I/O operations. The APIs are detailed
11 The big picture is that USB drivers can continue to ignore most DMA issues,
12 though they still must provide DMA-ready buffers (see
14 the 2.4 (and earlier) kernels, or they can now be DMA-aware.
16 DMA-aware usb drivers:
18 - New calls enable DMA-aware drivers, letting them allocate dma buffers and
25 - "usbcore" will map this DMA address, if a DMA-aware driver didn't do
29 - There's a new "generic DMA API", parts of which are usable by USB device
41 IOMMU to manage the DMA mappings. It can cost MUCH more to set up and
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| /linux/Documentation/i2c/ |
| H A D | dma-considerations.rst | 2 Linux I2C and DMA
6 transferred are small, it is not considered a prime user of DMA access. At this
7 time of writing, only 10% of I2C bus master drivers have DMA support
9 DMA for it will likely add more overhead than a plain PIO transfer.
11 Therefore, it is *not* mandatory that the buffer of an I2C message is DMA safe.
13 rarely used. However, it is recommended to use a DMA-safe buffer if your
14 message size is likely applicable for DMA. Most drivers have this threshold
18 I2C bus master driver is using USB as a bridge, then you need to have DMA
24 For clients, if you use a DMA safe buffer in i2c_msg, set the I2C_M_DMA_SAFE
25 flag with it. Then, the I2C core and drivers know they can safely operate DMA
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| /linux/drivers/dma/ti/ |
| H A D | Kconfig | 3 # Texas Instruments DMA drivers
7 tristate "Texas Instruments CPPI 4.1 DMA support"
11 The Communications Port Programming Interface (CPPI) 4.1 DMA engine
22 Enable support for the TI EDMA (Enhanced DMA) controller. This DMA
34 Enable support for the TI sDMA (System DMA or DMA4) controller. This
35 DMA engine is found on OMAP and DRA7xx parts.
47 Enable support for the TI UDMA (Unified DMA) controller. This
48 DMA engine is used in AM65x and j721e.
55 Say y here to support the K3 NAVSS DMA glue interface
|
| /linux/Documentation/devicetree/bindings/powerpc/4xx/ |
| H A D | ppc440spe-adma.txt | 1 PPC440SPe DMA/XOR (DMA Controller and XOR Accelerator)
4 are specified hereby. These are I2O/DMA, DMA and XOR nodes
5 for DMA engines and Memory Queue Module node. The latter is used
9 DMA devices.
28 ii) The DMA node
33 - cell-index : 1 cell, hardware index of the DMA engine
39 and DMA Error IRQ (on UIC1). The latter is common
40 for both DMA engines>.
|
| /linux/drivers/dma/qcom/ |
| H A D | Kconfig | 8 Enable support for the Qualcomm Application Data Mover (ADM) DMA
10 This controller provides DMA capabilities for both general purpose
14 tristate "QCOM BAM DMA support"
19 Enable support for the QCOM BAM DMA controller. This controller
20 provides DMA capabilities for a variety of on-chip devices.
23 tristate "Qualcomm Technologies GPI DMA support"
28 Enable support for the QCOM GPI DMA controller. This controller
29 provides DMA capabilities for a variety of peripheral buses such
40 Each DMA device requires one management interface driver
55 purpose slave DMA.
|
| /linux/Documentation/driver-api/rapidio/ |
| H A D | tsi721.rst | 12 To generate SRIO maintenance transactions this driver uses one of Tsi721 DMA
34 descriptors allocated for each registered Tsi721 DMA channel.
38 - DMA transactions queue size. Defines number of pending
39 transaction requests that can be accepted by each DMA channel.
43 - DMA channel selection mask. Bitmask that defines which hardware
44 DMA channels (0 ... 6) will be registered with DmaEngine core.
45 If bit is set to 1, the corresponding DMA channel will be registered.
46 DMA channels not selected by this mask will not be used by this device
68 3. DMA Engine Support
71 Tsi721 mport driver supports DMA data transfers between local system memory and
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| /linux/drivers/dma/mediatek/ |
| H A D | Kconfig | 4 tristate "MediaTek High-Speed DMA controller support"
9 Enable support for High-Speed DMA controller on MediaTek
17 tristate "MediaTek Command-Queue DMA controller support"
23 Enable support for Command-Queue DMA controller on MediaTek
35 Support for the UART DMA engine found on MediaTek MTK SoCs.
36 When SERIAL_8250_MT6577 is enabled, and if you want to use DMA,
37 you can enable the config. The DMA engine can only be used
|
| /linux/arch/sh/drivers/dma/ |
| H A D | Kconfig | 2 menu "DMA support"
6 bool "SuperH on-chip DMA controller (DMAC) support"
21 bool "SuperH DMA API support"
24 SH_DMA_API always enabled DMA API of used SuperH.
25 If you want to use DMA ENGINE, you must not enable this.
51 Say Y if you want to use Audio/USB DMA on your SH7760 board.
57 Selecting this will enable support for the PVR2 DMA controller.
67 tristate "G2 Bus DMA support"
70 This enables support for the DMA controller for the Dreamcast's
|
| /linux/drivers/dma/dw/ |
| H A D | Kconfig | 4 # DMA engine configuration for dw
12 tristate "Synopsys DesignWare AHB DMA platform driver"
16 Support the Synopsys DesignWare AHB DMA controller. This
25 the Synopsys DesignWare AHB DMA controller located on Renesas
29 tristate "Synopsys DesignWare AHB DMA PCI driver"
34 Support the Synopsys DesignWare AHB DMA controller on the
|