Lines Matching refs:DMA

5 hardware (DMA) access across multiple device drivers and subsystems, and
33 Shared DMA Buffers
39 Any device driver which wishes to be a part of DMA buffer sharing, can do so as
71 Mostly a DMA buffer file descriptor is simply an opaque object for userspace,
101 - Memory mapping the contents of the DMA buffer is also supported. See the
102 discussion below on `CPU Access to DMA Buffer Objects`_ for the full details.
104 - The DMA buffer FD is also pollable, see `Implicit Fence Poll Support`_ below for
107 - The DMA buffer FD also supports a few dma-buf-specific ioctls, see
108 `DMA Buffer ioctls`_ below for details.
110 Basic Operation and Device DMA Access
116 CPU Access to DMA Buffer Objects
128 DMA-BUF statistics
133 DMA Buffer ioctls
138 DMA-BUF locking convention
165 DMA Fences
169 :doc: DMA fences overview
171 DMA Fence Cross-Driver Contract
177 DMA Fence Signalling Annotations
183 DMA Fence Deadline Hints
189 DMA Fences Functions Reference
198 DMA Fence Array
207 DMA Fence Chain
216 DMA Fence unwrap
222 DMA Fence Sync File
231 DMA Fence Sync File uABI
237 Indefinite DMA Fences
252 are then imported as a DMA fence for integration into existing winsys
256 batch DMA fences for memory management instead of context preemption DMA
261 in-kernel DMA fences does not work, even when a fallback timeout is included to
264 * Only the kernel knows about all DMA fence dependencies, userspace is not aware
272 dependent upon DMA fences. If the kernel also support indefinite fences in the
273 kernel like a DMA fence, like any of the above proposal would, there is the
282 kernel [label="Kernel DMA Fences"]
300 * No future fences, proxy fences or userspace fences imported as DMA fences,
303 * No DMA fences that signal end of batchbuffer for command submission where
312 implications for DMA fences.
316 But memory allocations are not allowed to gate completion of DMA fences, which
317 means any workload using recoverable page faults cannot use DMA fences for
322 Linux rely on DMA fences, which means without an entirely new userspace stack
331 job with a DMA fence and a compute workload using recoverable page faults are
338 allocation is waiting for the DMA fence of the 3D workload to complete.
346 - DMA fence workloads and workloads which need page fault handling have
349 reservations for DMA fence workloads.
352 hardware resources for DMA fence workloads when they are in-flight. This must
353 cover the time from when the DMA fence is visible to other threads up to
358 requiring DMA fences or jobs requiring page fault handling: This means all DMA
360 inserted into the scheduler queue. And vice versa, before a DMA fence can be
366 memory blocks or runtime tracking of the full dependency graph of all DMA
373 GPUs do not have any impact. This allows us to keep using DMA fences internally
377 In some ways this page fault problem is a special case of the `Infinite DMA
379 depend on DMA fences, but not the other way around. And not even the page fault