1*9b5d2a4fSGeert UytterhoevenAnalog Devices AXI-DMAC DMA controller 243bcad2bSLars-Peter Clausen 343bcad2bSLars-Peter ClausenRequired properties: 443bcad2bSLars-Peter Clausen - compatible: Must be "adi,axi-dmac-1.00.a". 543bcad2bSLars-Peter Clausen - reg: Specification for the controllers memory mapped register map. 643bcad2bSLars-Peter Clausen - interrupts: Specification for the controllers interrupt. 743bcad2bSLars-Peter Clausen - clocks: Phandle and specifier to the controllers AXI interface clock 843bcad2bSLars-Peter Clausen - #dma-cells: Must be 1. 943bcad2bSLars-Peter Clausen 1043bcad2bSLars-Peter ClausenRequired sub-nodes: 1143bcad2bSLars-Peter Clausen - adi,channels: This sub-node must contain a sub-node for each DMA channel. For 1243bcad2bSLars-Peter Clausen the channel sub-nodes the following bindings apply. They must match the 1343bcad2bSLars-Peter Clausen configuration options of the peripheral as it was instantiated. 1443bcad2bSLars-Peter Clausen 1543bcad2bSLars-Peter ClausenRequired properties for adi,channels sub-node: 1643bcad2bSLars-Peter Clausen - #size-cells: Must be 0 1743bcad2bSLars-Peter Clausen - #address-cells: Must be 1 1843bcad2bSLars-Peter Clausen 1943bcad2bSLars-Peter ClausenRequired channel sub-node properties: 2043bcad2bSLars-Peter Clausen - reg: Which channel this node refers to. 2143bcad2bSLars-Peter Clausen - adi,source-bus-width, 2243bcad2bSLars-Peter Clausen adi,destination-bus-width: Width of the source or destination bus in bits. 2343bcad2bSLars-Peter Clausen - adi,source-bus-type, 2443bcad2bSLars-Peter Clausen adi,destination-bus-type: Type of the source or destination bus. Must be one 2543bcad2bSLars-Peter Clausen of the following: 2643bcad2bSLars-Peter Clausen 0 (AXI_DMAC_TYPE_AXI_MM): Memory mapped AXI interface 2743bcad2bSLars-Peter Clausen 1 (AXI_DMAC_TYPE_AXI_STREAM): Streaming AXI interface 2843bcad2bSLars-Peter Clausen 2 (AXI_DMAC_TYPE_AXI_FIFO): FIFO interface 2943bcad2bSLars-Peter Clausen 3056009f0dSLars-Peter ClausenDeprecated optional channel properties: 3156009f0dSLars-Peter Clausen - adi,length-width: Width of the DMA transfer length register. 3243bcad2bSLars-Peter Clausen - adi,cyclic: Must be set if the channel supports hardware cyclic DMA 3343bcad2bSLars-Peter Clausen transfers. 3443bcad2bSLars-Peter Clausen - adi,2d: Must be set if the channel supports hardware 2D DMA transfers. 3543bcad2bSLars-Peter Clausen 3643bcad2bSLars-Peter ClausenDMA clients connected to the AXI-DMAC DMA controller must use the format 3743bcad2bSLars-Peter Clausendescribed in the dma.txt file using a one-cell specifier. The value of the 3843bcad2bSLars-Peter Clausenspecifier refers to the DMA channel index. 3943bcad2bSLars-Peter Clausen 4043bcad2bSLars-Peter ClausenExample: 4143bcad2bSLars-Peter Clausen 4243bcad2bSLars-Peter Clausendma: dma@7c420000 { 4343bcad2bSLars-Peter Clausen compatible = "adi,axi-dmac-1.00.a"; 4443bcad2bSLars-Peter Clausen reg = <0x7c420000 0x10000>; 4543bcad2bSLars-Peter Clausen interrupts = <0 57 0>; 4643bcad2bSLars-Peter Clausen clocks = <&clkc 16>; 4743bcad2bSLars-Peter Clausen #dma-cells = <1>; 4843bcad2bSLars-Peter Clausen 4943bcad2bSLars-Peter Clausen adi,channels { 5043bcad2bSLars-Peter Clausen #size-cells = <0>; 5143bcad2bSLars-Peter Clausen #address-cells = <1>; 5243bcad2bSLars-Peter Clausen 5343bcad2bSLars-Peter Clausen dma-channel@0 { 5443bcad2bSLars-Peter Clausen reg = <0>; 5543bcad2bSLars-Peter Clausen adi,source-bus-width = <32>; 5643bcad2bSLars-Peter Clausen adi,source-bus-type = <ADI_AXI_DMAC_TYPE_MM_AXI>; 5743bcad2bSLars-Peter Clausen adi,destination-bus-width = <64>; 5843bcad2bSLars-Peter Clausen adi,destination-bus-type = <ADI_AXI_DMAC_TYPE_FIFO>; 5943bcad2bSLars-Peter Clausen }; 6043bcad2bSLars-Peter Clausen }; 6143bcad2bSLars-Peter Clausen}; 62