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Searched refs:DISPLAY_VER (Results 1 – 25 of 77) sorted by relevance

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/linux/drivers/gpu/drm/i915/display/
H A Dintel_display_device.h143 #define HAS_4TILE(__display) ((__display)->platform.dg2 || DISPLAY_VER(__display) >= 14)
144 #define HAS_ASYNC_FLIPS(__display) (DISPLAY_VER(__display) >= 5)
145 #define HAS_BIGJOINER(__display) (DISPLAY_VER(__display) >= 11 && HAS_DSC(__display))
154 #define HAS_DMC_WAKELOCK(__display) (DISPLAY_VER(__display) >= 20)
155 #define HAS_DOUBLE_BUFFERED_M_N(__display) (DISPLAY_VER(__display) >= 9 || (__display)->platform.br…
156 #define HAS_DOUBLE_WIDE(__display) (DISPLAY_VER(__display) < 4)
158 #define HAS_DP20(__display) ((__display)->platform.dg2 || DISPLAY_VER(__display) >= 14)
159 #define HAS_DPT(__display) (DISPLAY_VER(__display) >= 13)
162 #define HAS_DSC_MST(__display) (DISPLAY_VER(__display) >= 12 && HAS_DSC(__display))
165 #define HAS_FW_BLC(__display) (DISPLAY_VER(__display) >= 3)
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H A Di9xx_display_sr.c20 if (DISPLAY_VER(display) == 2 && display->platform.mobile) { in i9xx_display_save_swf()
27 } else if (DISPLAY_VER(display) == 2) { in i9xx_display_save_swf()
45 if (DISPLAY_VER(display) == 2 && display->platform.mobile) { in i9xx_display_restore_swf()
52 } else if (DISPLAY_VER(display) == 2) { in i9xx_display_restore_swf()
73 if (DISPLAY_VER(display) <= 4) in i9xx_display_sr_save()
76 if (DISPLAY_VER(display) == 4) in i9xx_display_sr_save()
91 if (DISPLAY_VER(display) == 4) in i9xx_display_sr_restore()
95 if (DISPLAY_VER(display) <= 4) in i9xx_display_sr_restore()
H A Di9xx_plane.c123 else if (DISPLAY_VER(dev_priv) >= 4) in i9xx_plane_has_fbc()
145 else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) in i9xx_plane_has_windowing()
147 else if (DISPLAY_VER(dev_priv) == 4) in i9xx_plane_has_windowing()
214 if (DISPLAY_VER(dev_priv) >= 4 && in i9xx_plane_ctl()
253 if (DISPLAY_VER(dev_priv) >= 4) in i9xx_check_plane_surface()
270 if (DISPLAY_VER(dev_priv) >= 4 && fb->modifier == I915_FORMAT_MOD_X_TILED) { in i9xx_check_plane_surface()
309 } else if (DISPLAY_VER(dev_priv) >= 4 && in i9xx_check_plane_surface()
367 if (DISPLAY_VER(dev_priv) < 5) in i9xx_plane_ctl_crtc()
431 if (DISPLAY_VER(dev_priv) < 4) { in i9xx_plane_update_noarm()
469 if (DISPLAY_VER(dev_priv) >= 4) in i9xx_plane_update_arm()
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H A Dintel_fbc.c172 if (DISPLAY_VER(display) >= 11) in skl_fbc_min_cfb_stride()
195 if (DISPLAY_VER(display) >= 9) in _intel_fbc_cfb_stride()
220 if (DISPLAY_VER(display) >= 8) in intel_fbc_max_cfb_height()
222 else if (DISPLAY_VER(display) >= 5 || IS_G4X(i915)) in intel_fbc_max_cfb_height()
257 (DISPLAY_VER(display) == 9 && fb->modifier == DRM_FORMAT_MOD_LINEAR)) in intel_fbc_override_cfb_stride()
281 if (DISPLAY_VER(display) == 2) in i8xx_fbc_ctl()
344 if (DISPLAY_VER(display) == 4) { in i8xx_fbc_activate()
454 if (DISPLAY_VER(display) < 6) in g4x_dpfc_ctl()
643 if (DISPLAY_VER(display) >= 20) in ivb_dpfc_ctl()
660 if (DISPLAY_VER(display) >= 10) in ivb_fbc_activate()
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H A Dskl_universal_plane.c240 if (DISPLAY_VER(display) >= 13 || HAS_D12_PLANE_MINIMIZATION(display)) in icl_nv12_y_plane_mask()
249 return DISPLAY_VER(dev_priv) >= 11 && in icl_is_nv12_y_plane()
260 return DISPLAY_VER(dev_priv) >= 11 && in icl_is_hdr_plane()
785 if (DISPLAY_VER(display) < 11) in skl_write_plane_wm()
789 if (DISPLAY_VER(display) >= 30) in skl_write_plane_wm()
1081 if (DISPLAY_VER(dev_priv) >= 10) in skl_plane_ctl_crtc()
1105 if (DISPLAY_VER(dev_priv) < 10) { in skl_plane_ctl()
1120 if (DISPLAY_VER(dev_priv) >= 11) in skl_plane_ctl()
1130 if (DISPLAY_VER(dev_priv) == 13) in skl_plane_ctl()
1141 if (DISPLAY_VER(dev_priv) >= 11) in glk_plane_color_ctl_crtc()
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H A Dintel_psr.c286 return DISPLAY_VER(display) >= 12 ? TGL_PSR_ERROR : in psr_irq_psr_error_bit_get()
294 return DISPLAY_VER(display) >= 12 ? TGL_PSR_POST_EXIT : in psr_irq_post_exit_bit_get()
302 return DISPLAY_VER(display) >= 12 ? TGL_PSR_PRE_ENTRY : in psr_irq_pre_entry_bit_get()
310 return DISPLAY_VER(display) >= 12 ? TGL_PSR_MASK : in psr_irq_mask_get()
317 if (DISPLAY_VER(display) >= 8) in psr_ctl_reg()
326 if (DISPLAY_VER(display) >= 8) in psr_debug_reg()
335 if (DISPLAY_VER(display) >= 8) in psr_perf_cnt_reg()
344 if (DISPLAY_VER(display) >= 8) in psr_status_reg()
353 if (DISPLAY_VER(display) >= 12) in psr_imr_reg()
362 if (DISPLAY_VER(display) >= 12) in psr_iir_reg()
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H A Dintel_display_irq.c193 if (DISPLAY_VER(dev_priv) < 5) in i915_pipestat_enable_mask()
305 if (DISPLAY_VER(dev_priv) >= 4) in i915_enable_asle_pipestat()
336 (DISPLAY_VER(dev_priv) >= 8 && pipe_crc->skipped == 1)) { in display_pipe_crc_irq_handler()
397 if (DISPLAY_VER(dev_priv) >= 3) in i9xx_pipe_crc_irq_handler()
403 if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) in i9xx_pipe_crc_irq_handler()
746 if (DISPLAY_VER(dev_priv) == 5 && de_iir & DE_PCU_EVENT) in ilk_display_irq_handler()
805 if (DISPLAY_VER(dev_priv) >= 20) in gen8_de_port_aux_mask()
807 else if (DISPLAY_VER(dev_priv) >= 14) in gen8_de_port_aux_mask()
810 else if (DISPLAY_VER(dev_priv) >= 13) in gen8_de_port_aux_mask()
820 else if (DISPLAY_VER(dev_priv) >= 12) in gen8_de_port_aux_mask()
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H A Dintel_ddi.c110 return DISPLAY_VER(i915) < 10 && !IS_BROXTON(i915); in has_buf_trans_select()
115 return DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915); in has_iboost()
214 if (DISPLAY_VER(dev_priv) < 10) { in intel_wait_ddi_buf_active()
219 if (DISPLAY_VER(dev_priv) >= 14) { in intel_wait_ddi_buf_active()
223 } else if (DISPLAY_VER(dev_priv) >= 12) { in intel_wait_ddi_buf_active()
232 if (DISPLAY_VER(dev_priv) >= 14) in intel_wait_ddi_buf_active()
347 if (DISPLAY_VER(i915) >= 14) { in intel_ddi_init_dp_buf_reg()
498 if (DISPLAY_VER(dev_priv) >= 12) in intel_ddi_transcoder_func_reg_val_get()
560 if (DISPLAY_VER(dev_priv) >= 14) in intel_ddi_transcoder_func_reg_val_get()
573 if (DISPLAY_VER(dev_priv) >= 12) { in intel_ddi_transcoder_func_reg_val_get()
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H A Dintel_alpm.c179 if (DISPLAY_VER(display) < 20) in _lnl_compute_alpm_params()
219 if (DISPLAY_VER(display) >= 12) in io_buffer_wake_time()
241 if (DISPLAY_VER(display) >= 20) in intel_alpm_compute_params()
243 else if (DISPLAY_VER(display) >= 12) in intel_alpm_compute_params()
282 if (DISPLAY_VER(display) < 20) in intel_alpm_lobf_compute_config()
319 if (DISPLAY_VER(display) < 20 || in lnl_alpm_configure()
411 if (DISPLAY_VER(display) < 20 || in intel_alpm_lobf_debugfs_add()
H A Dintel_pmdemand.c150 if (DISPLAY_VER(display) < 14) in intel_pmdemand_update_phys_mask()
172 if (DISPLAY_VER(display) < 14) in intel_pmdemand_update_port_clock()
315 if (DISPLAY_VER(display) < 30) { in intel_pmdemand_needs_update()
347 if (DISPLAY_VER(display) < 14) in intel_pmdemand_atomic_check()
369 if (DISPLAY_VER(display) < 30) { in intel_pmdemand_atomic_check()
427 if (DISPLAY_VER(display) < 14) in intel_pmdemand_init_pmdemand_params()
456 if (DISPLAY_VER(display) >= 30) { in intel_pmdemand_init_pmdemand_params()
495 if (DISPLAY_VER(display) >= 30) in intel_pmdemand_program_dbuf()
559 if (DISPLAY_VER(display) >= 30) { in intel_pmdemand_update_params()
639 if (DISPLAY_VER(display) < 14) in intel_pmdemand_pre_plane_update()
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H A Dskl_watermark.c74 return DISPLAY_VER(i915) == 9; in skl_needs_memory_bw_wa()
90 if (DISPLAY_VER(display) >= 14) { in intel_sagv_block_time()
96 } else if (DISPLAY_VER(display) >= 12) { in intel_sagv_block_time()
109 } else if (DISPLAY_VER(display) == 11) { in intel_sagv_block_time()
129 if (DISPLAY_VER(display) < 11) in intel_sagv_init()
328 if (DISPLAY_VER(i915) >= 11) in intel_sagv_pre_plane_update()
348 if (DISPLAY_VER(i915) >= 11) in intel_sagv_post_plane_update()
434 if (DISPLAY_VER(i915) >= 12) in intel_crtc_can_enable_sagv()
443 if (DISPLAY_VER(i915) < 11 && in intel_can_enable_sagv()
489 DISPLAY_VER(i915) >= 12 && in intel_compute_sagv_mask()
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H A Dintel_bw.c92 sp->dclk = DIV_ROUND_UP((16667 * dclk) + (DISPLAY_VER(dev_priv) >= 12 ? 500 : 0), in icl_pcode_read_qgv_point_info()
156 if (DISPLAY_VER(dev_priv) >= 14) in icl_pcode_restrict_qgv_points()
207 if (DISPLAY_VER(dev_priv) >= 14) in intel_read_qgv_point_info()
225 if (DISPLAY_VER(dev_priv) >= 14) { in icl_get_qgv_points()
253 } else if (DISPLAY_VER(dev_priv) >= 12) { in icl_get_qgv_points()
287 } else if (DISPLAY_VER(dev_priv) == 11) { in icl_get_qgv_points()
490 if (DISPLAY_VER(dev_priv) < 14 && in tgl_get_bw_info()
496 if (num_channels < qi.max_numchannels && DISPLAY_VER(dev_priv) >= 12) in tgl_get_bw_info()
499 if (DISPLAY_VER(dev_priv) >= 12 && num_channels > qi.max_numchannels) in tgl_get_bw_info()
730 if (DISPLAY_VER(i915) >= 12) in icl_qgv_bw()
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H A Dintel_display_power.c937 if (DISPLAY_VER(display) >= 20) in get_allowed_dc_mask()
943 else if (DISPLAY_VER(display) >= 12) in get_allowed_dc_mask()
947 else if (DISPLAY_VER(display) >= 9) in get_allowed_dc_mask()
958 DISPLAY_VER(display) >= 11 ? DC_STATE_EN_DC9 : 0; in get_allowed_dc_mask()
1105 if (DISPLAY_VER(display) >= 14) in gen9_dbuf_enable()
1121 if (DISPLAY_VER(display) >= 14) in gen9_dbuf_disable()
1143 if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) in icl_mbus_init()
1160 if (DISPLAY_VER(display) == 12) in icl_mbus_init()
1429 if (DISPLAY_VER(display) >= 14) in intel_pch_reset_handshake()
1636 if (DISPLAY_VER(display) == 12) in tgl_bw_buddy_init()
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H A Dintel_cx0_phy_regs.h45 (DISPLAY_VER(i915__) >= 20 ? \
65 (DISPLAY_VER(i915__) >= 20 ? \
96 (DISPLAY_VER(i915__) >= 20 ? \
121 (DISPLAY_VER(i915__) >= 20 ? \
144 (DISPLAY_VER(i915__) >= 20 ? \
167 (DISPLAY_VER(i915__) >= 20 ? \
184 (DISPLAY_VER(i915__) >= 20 ? \
H A Dintel_crtc.c116 if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) in intel_crtc_max_vblank_count()
118 else if (DISPLAY_VER(dev_priv) >= 3) in intel_crtc_max_vblank_count()
321 if (DISPLAY_VER(dev_priv) >= 9) in intel_crtc_init()
336 if (DISPLAY_VER(dev_priv) >= 9) in intel_crtc_init()
358 else if (DISPLAY_VER(dev_priv) == 4) in intel_crtc_init()
362 else if (DISPLAY_VER(dev_priv) == 3) in intel_crtc_init()
367 if (DISPLAY_VER(dev_priv) >= 8) in intel_crtc_init()
379 if (DISPLAY_VER(dev_priv) >= 11) in intel_crtc_init()
669 if (DISPLAY_VER(dev_priv) >= 11 && in intel_pipe_update_end()
H A Dintel_pfit.c73 if (DISPLAY_VER(display) >= 8) { in intel_pch_pfit_check_src_size()
76 } else if (DISPLAY_VER(display) >= 7) { in intel_pch_pfit_check_src_size()
255 if (DISPLAY_VER(display) >= 9) in pch_panel_fitting()
422 if (DISPLAY_VER(display) >= 4) in intel_gmch_pfit_check_timings()
492 if (DISPLAY_VER(display) >= 4) in gmch_panel_fitting()
506 if (DISPLAY_VER(display) >= 4) in gmch_panel_fitting()
522 if (DISPLAY_VER(display) >= 4) in gmch_panel_fitting()
532 if (DISPLAY_VER(display) < 4 && crtc_state->pipe_bpp == 18) in gmch_panel_fitting()
H A Dintel_display_wa.c36 else if (DISPLAY_VER(i915) == 12) in intel_display_wa_apply()
38 else if (DISPLAY_VER(i915) == 11) in intel_display_wa_apply()
H A Dintel_dpt_common.c17 if (DISPLAY_VER(i915) == 14) { in intel_dpt_configure()
30 } else if (DISPLAY_VER(i915) == 13) { in intel_dpt_configure()
H A Dskl_scaler.c134 if (DISPLAY_VER(display) >= 9 && crtc_state->hw.enable && in skl_update_scaler()
178 if (DISPLAY_VER(display) < 11) { in skl_update_scaler()
183 } else if (DISPLAY_VER(display) < 12) { in skl_update_scaler()
188 } else if (DISPLAY_VER(display) < 14) { in skl_update_scaler()
335 if (DISPLAY_VER(display) == 9) { in intel_atomic_setup_scaler()
353 } else if (DISPLAY_VER(display) >= 10) { in intel_atomic_setup_scaler()
387 if (DISPLAY_VER(display) >= 14) { in intel_atomic_setup_scaler()
400 } else if (DISPLAY_VER(display) >= 10 || in intel_atomic_setup_scaler()
472 if (!plane_state && DISPLAY_VER(display) >= 10) in setup_plane_scaler()
H A Dintel_audio.c193 return (DISPLAY_VER(i915) == 20 || IS_BATTLEMAGE(i915)); in needs_wa_14020863754()
209 if (DISPLAY_VER(i915) < 12 && adjusted_mode->crtc_clock > 148500) in audio_config_hdmi_pixel_clock()
505 if (DISPLAY_VER(i915) < 11) in enable_audio_dsc_wa()
510 if (DISPLAY_VER(i915) == 11) in enable_audio_dsc_wa()
512 else if (DISPLAY_VER(i915) >= 12) in enable_audio_dsc_wa()
891 else if (IS_HASWELL(i915) || DISPLAY_VER(i915) >= 8) in intel_audio_hooks_init()
902 if (DISPLAY_VER(i915) >= 13) in intel_audio_cdclk_change_pre()
916 if (DISPLAY_VER(i915) >= 13) { in intel_audio_cdclk_change_post()
1000 if (DISPLAY_VER(display) == 10) { in intel_audio_min_cdclk()
1003 } else if (DISPLAY_VER(display) == 9 || IS_BROADWELL(dev_priv)) { in intel_audio_min_cdclk()
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H A Dintel_cdclk.c1670 else if (DISPLAY_VER(display) >= 11) in bxt_de_pll_readout()
1690 if (DISPLAY_VER(display) >= 11) in bxt_de_pll_readout()
1707 if (DISPLAY_VER(display) >= 12) in bxt_get_cdclk()
1709 else if (DISPLAY_VER(display) >= 11) in bxt_get_cdclk()
1756 if (DISPLAY_VER(display) >= 20) in bxt_get_cdclk()
1851 if (DISPLAY_VER(display) >= 12) { in bxt_cdclk_cd2x_pipe()
1856 } else if (DISPLAY_VER(display) >= 11) { in bxt_cdclk_cd2x_pipe()
1954 return DISPLAY_VER(display) >= 20; in mdclk_source_is_cdclk_pll()
2091 if (DISPLAY_VER(display) >= 20) in bxt_cdclk_ctl()
2110 } else if (DISPLAY_VER(display) >= 11) { in _bxt_set_cdclk()
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H A Dintel_dmc.c204 } else if (DISPLAY_VER(display) == 11) { in dmc_firmware_default()
432 if (DISPLAY_VER(display) < 12) in disable_all_event_handlers()
482 if (DISPLAY_VER(display) >= 14 && enable) in pipedmc_clock_gating_wa()
484 else if (DISPLAY_VER(display) == 13) in pipedmc_clock_gating_wa()
495 if (DISPLAY_VER(display) >= 14) in intel_dmc_enable_pipe()
508 if (DISPLAY_VER(display) >= 14) in intel_dmc_disable_pipe()
724 } else if (DISPLAY_VER(display) >= 13) { in dmc_mmio_addr_sanity_check()
727 } else if (DISPLAY_VER(display) >= 12) { in dmc_mmio_addr_sanity_check()
1256 str_yes_no(DISPLAY_VER(display) >= 12)); in intel_dmc_debugfs_status_show()
1261 DISPLAY_VER(display) >= 14)); in intel_dmc_debugfs_status_show()
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H A Dintel_dp_aux.c23 if (DISPLAY_VER(display) >= 13 && aux_ch >= AUX_CH_D_XELPD) in aux_ch_name()
25 else if (DISPLAY_VER(display) >= 12 && aux_ch >= AUX_CH_USBC1) in aux_ch_name()
231 if (DISPLAY_VER(display) >= 14) in skl_get_aux_send_ctl()
781 if (DISPLAY_VER(display) >= 14) { in intel_dp_aux_init()
784 } else if (DISPLAY_VER(display) >= 12) { in intel_dp_aux_init()
787 } else if (DISPLAY_VER(display) >= 9) { in intel_dp_aux_init()
801 if (DISPLAY_VER(display) >= 9) in intel_dp_aux_init()
810 if (DISPLAY_VER(display) >= 9) in intel_dp_aux_init()
832 if (DISPLAY_VER(display) == 9 && encoder->port == PORT_E) in default_aux_ch()
H A Dintel_pipe_crc.c411 if (DISPLAY_VER(dev_priv) == 2) in get_new_crc_ctl_reg()
413 else if (DISPLAY_VER(dev_priv) < 5) in get_new_crc_ctl_reg()
419 else if (DISPLAY_VER(dev_priv) < 9) in get_new_crc_ctl_reg()
541 if (DISPLAY_VER(dev_priv) == 2) in intel_is_valid_crc_source()
543 else if (DISPLAY_VER(dev_priv) < 5) in intel_is_valid_crc_source()
549 else if (DISPLAY_VER(dev_priv) < 9) in intel_is_valid_crc_source()
H A Dintel_display_device.c1720 else if (DISPLAY_VER(display) >= 11) { in __intel_display_device_info_runtime_init()
1723 } else if (DISPLAY_VER(display) >= 9) { in __intel_display_device_info_runtime_init()
1729 if (DISPLAY_VER(display) >= 13 || HAS_D12_PLANE_MINIMIZATION(display)) in __intel_display_device_info_runtime_init()
1732 else if (DISPLAY_VER(display) >= 11) in __intel_display_device_info_runtime_init()
1735 else if (DISPLAY_VER(display) == 10) in __intel_display_device_info_runtime_init()
1754 } else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) { in __intel_display_device_info_runtime_init()
1759 if ((display->platform.dgfx || DISPLAY_VER(display) >= 14) && in __intel_display_device_info_runtime_init()
1790 } else if (DISPLAY_VER(display) >= 9) { in __intel_display_device_info_runtime_init()
1809 if (DISPLAY_VER(display) >= 12 && in __intel_display_device_info_runtime_init()
1822 if (display->platform.dg2 || DISPLAY_VER(display) < 13) { in __intel_display_device_info_runtime_init()
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