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Searched refs:CLK_MM_MDP_RSZ1 (Results 1 – 19 of 19) sorted by relevance

/linux/drivers/clk/mediatek/
H A Dclk-mt6765-mm.c29 GATE_MM(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_ck", 3),
H A Dclk-mt8167-mm.c43 GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "smi_mm", 5),
H A Dclk-mt6795-mm.c39 GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 6),
H A Dclk-mt6797-mm.c40 GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 7),
H A Dclk-mt8183-mm.c51 GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 15),
H A Dclk-mt6779-mm.c51 GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 15),
H A Dclk-mt8173-mm.c43 GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 6),
H A Dclk-mt2712-mm.c50 GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 6),
H A Dclk-mt8196-disp0.c138 GATE_HWV_MM1(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "disp", 19),
/linux/include/dt-bindings/clock/
H A Dmt8167-clk.h84 #define CLK_MM_MDP_RSZ1 5 macro
H A Dmt6797-clk.h222 #define CLK_MM_MDP_RSZ1 8 macro
H A Dmediatek,mt6795-clk.h225 #define CLK_MM_MDP_RSZ1 6 macro
H A Dmt8173-clk.h254 #define CLK_MM_MDP_RSZ1 7 macro
H A Dmt6765-clk.h254 #define CLK_MM_MDP_RSZ1 3 macro
H A Dmt6779-clk.h356 #define CLK_MM_MDP_RSZ1 16 macro
H A Dmt8183-clk.h324 #define CLK_MM_MDP_RSZ1 15 macro
H A Dmt2712-clk.h307 #define CLK_MM_MDP_RSZ1 6 macro
H A Dmt2701-clk.h365 #define CLK_MM_MDP_RSZ1 13 macro
H A Dmediatek,mt8196-clock.h435 #define CLK_MM_MDP_RSZ1 51 macro