1*1802d0beSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2df0225a4SMars Cheng /* 3df0225a4SMars Cheng * Copyright (c) 2017 MediaTek Inc. 4df0225a4SMars Cheng * Author: Kevin Chen <kevin-cw.chen@mediatek.com> 5df0225a4SMars Cheng */ 6df0225a4SMars Cheng 7df0225a4SMars Cheng #ifndef _DT_BINDINGS_CLK_MT6797_H 8df0225a4SMars Cheng #define _DT_BINDINGS_CLK_MT6797_H 9df0225a4SMars Cheng 10df0225a4SMars Cheng /* TOPCKGEN */ 11df0225a4SMars Cheng #define CLK_TOP_MUX_ULPOSC_AXI_CK_MUX_PRE 1 12df0225a4SMars Cheng #define CLK_TOP_MUX_ULPOSC_AXI_CK_MUX 2 13df0225a4SMars Cheng #define CLK_TOP_MUX_AXI 3 14df0225a4SMars Cheng #define CLK_TOP_MUX_MEM 4 15df0225a4SMars Cheng #define CLK_TOP_MUX_DDRPHYCFG 5 16df0225a4SMars Cheng #define CLK_TOP_MUX_MM 6 17df0225a4SMars Cheng #define CLK_TOP_MUX_PWM 7 18df0225a4SMars Cheng #define CLK_TOP_MUX_VDEC 8 19df0225a4SMars Cheng #define CLK_TOP_MUX_VENC 9 20df0225a4SMars Cheng #define CLK_TOP_MUX_MFG 10 21df0225a4SMars Cheng #define CLK_TOP_MUX_CAMTG 11 22df0225a4SMars Cheng #define CLK_TOP_MUX_UART 12 23df0225a4SMars Cheng #define CLK_TOP_MUX_SPI 13 24df0225a4SMars Cheng #define CLK_TOP_MUX_ULPOSC_SPI_CK_MUX 14 25df0225a4SMars Cheng #define CLK_TOP_MUX_USB20 15 26df0225a4SMars Cheng #define CLK_TOP_MUX_MSDC50_0_HCLK 16 27df0225a4SMars Cheng #define CLK_TOP_MUX_MSDC50_0 17 28df0225a4SMars Cheng #define CLK_TOP_MUX_MSDC30_1 18 29df0225a4SMars Cheng #define CLK_TOP_MUX_MSDC30_2 19 30df0225a4SMars Cheng #define CLK_TOP_MUX_AUDIO 20 31df0225a4SMars Cheng #define CLK_TOP_MUX_AUD_INTBUS 21 32df0225a4SMars Cheng #define CLK_TOP_MUX_PMICSPI 22 33df0225a4SMars Cheng #define CLK_TOP_MUX_SCP 23 34df0225a4SMars Cheng #define CLK_TOP_MUX_ATB 24 35df0225a4SMars Cheng #define CLK_TOP_MUX_MJC 25 36df0225a4SMars Cheng #define CLK_TOP_MUX_DPI0 26 37df0225a4SMars Cheng #define CLK_TOP_MUX_AUD_1 27 38df0225a4SMars Cheng #define CLK_TOP_MUX_AUD_2 28 39df0225a4SMars Cheng #define CLK_TOP_MUX_SSUSB_TOP_SYS 29 40df0225a4SMars Cheng #define CLK_TOP_MUX_SPM 30 41df0225a4SMars Cheng #define CLK_TOP_MUX_BSI_SPI 31 42df0225a4SMars Cheng #define CLK_TOP_MUX_AUDIO_H 32 43df0225a4SMars Cheng #define CLK_TOP_MUX_ANC_MD32 33 44df0225a4SMars Cheng #define CLK_TOP_MUX_MFG_52M 34 45df0225a4SMars Cheng #define CLK_TOP_SYSPLL_CK 35 46df0225a4SMars Cheng #define CLK_TOP_SYSPLL_D2 36 47df0225a4SMars Cheng #define CLK_TOP_SYSPLL1_D2 37 48df0225a4SMars Cheng #define CLK_TOP_SYSPLL1_D4 38 49df0225a4SMars Cheng #define CLK_TOP_SYSPLL1_D8 39 50df0225a4SMars Cheng #define CLK_TOP_SYSPLL1_D16 40 51df0225a4SMars Cheng #define CLK_TOP_SYSPLL_D3 41 52df0225a4SMars Cheng #define CLK_TOP_SYSPLL_D3_D3 42 53df0225a4SMars Cheng #define CLK_TOP_SYSPLL2_D2 43 54df0225a4SMars Cheng #define CLK_TOP_SYSPLL2_D4 44 55df0225a4SMars Cheng #define CLK_TOP_SYSPLL2_D8 45 56df0225a4SMars Cheng #define CLK_TOP_SYSPLL_D5 46 57df0225a4SMars Cheng #define CLK_TOP_SYSPLL3_D2 47 58df0225a4SMars Cheng #define CLK_TOP_SYSPLL3_D4 48 59df0225a4SMars Cheng #define CLK_TOP_SYSPLL_D7 49 60df0225a4SMars Cheng #define CLK_TOP_SYSPLL4_D2 50 61df0225a4SMars Cheng #define CLK_TOP_SYSPLL4_D4 51 62df0225a4SMars Cheng #define CLK_TOP_UNIVPLL_CK 52 63df0225a4SMars Cheng #define CLK_TOP_UNIVPLL_D7 53 64df0225a4SMars Cheng #define CLK_TOP_UNIVPLL_D26 54 65df0225a4SMars Cheng #define CLK_TOP_SSUSB_PHY_48M_CK 55 66df0225a4SMars Cheng #define CLK_TOP_USB_PHY48M_CK 56 67df0225a4SMars Cheng #define CLK_TOP_UNIVPLL_D2 57 68df0225a4SMars Cheng #define CLK_TOP_UNIVPLL1_D2 58 69df0225a4SMars Cheng #define CLK_TOP_UNIVPLL1_D4 59 70df0225a4SMars Cheng #define CLK_TOP_UNIVPLL1_D8 60 71df0225a4SMars Cheng #define CLK_TOP_UNIVPLL_D3 61 72df0225a4SMars Cheng #define CLK_TOP_UNIVPLL2_D2 62 73df0225a4SMars Cheng #define CLK_TOP_UNIVPLL2_D4 63 74df0225a4SMars Cheng #define CLK_TOP_UNIVPLL2_D8 64 75df0225a4SMars Cheng #define CLK_TOP_UNIVPLL_D5 65 76df0225a4SMars Cheng #define CLK_TOP_UNIVPLL3_D2 66 77df0225a4SMars Cheng #define CLK_TOP_UNIVPLL3_D4 67 78df0225a4SMars Cheng #define CLK_TOP_UNIVPLL3_D8 68 79df0225a4SMars Cheng #define CLK_TOP_ULPOSC_CK_ORG 69 80df0225a4SMars Cheng #define CLK_TOP_ULPOSC_CK 70 81df0225a4SMars Cheng #define CLK_TOP_ULPOSC_D2 71 82df0225a4SMars Cheng #define CLK_TOP_ULPOSC_D3 72 83df0225a4SMars Cheng #define CLK_TOP_ULPOSC_D4 73 84df0225a4SMars Cheng #define CLK_TOP_ULPOSC_D8 74 85df0225a4SMars Cheng #define CLK_TOP_ULPOSC_D10 75 86df0225a4SMars Cheng #define CLK_TOP_APLL1_CK 76 87df0225a4SMars Cheng #define CLK_TOP_APLL2_CK 77 88df0225a4SMars Cheng #define CLK_TOP_MFGPLL_CK 78 89df0225a4SMars Cheng #define CLK_TOP_MFGPLL_D2 79 90df0225a4SMars Cheng #define CLK_TOP_IMGPLL_CK 80 91df0225a4SMars Cheng #define CLK_TOP_IMGPLL_D2 81 92df0225a4SMars Cheng #define CLK_TOP_IMGPLL_D4 82 93df0225a4SMars Cheng #define CLK_TOP_CODECPLL_CK 83 94df0225a4SMars Cheng #define CLK_TOP_CODECPLL_D2 84 95df0225a4SMars Cheng #define CLK_TOP_VDECPLL_CK 85 96df0225a4SMars Cheng #define CLK_TOP_TVDPLL_CK 86 97df0225a4SMars Cheng #define CLK_TOP_TVDPLL_D2 87 98df0225a4SMars Cheng #define CLK_TOP_TVDPLL_D4 88 99df0225a4SMars Cheng #define CLK_TOP_TVDPLL_D8 89 100df0225a4SMars Cheng #define CLK_TOP_TVDPLL_D16 90 101df0225a4SMars Cheng #define CLK_TOP_MSDCPLL_CK 91 102df0225a4SMars Cheng #define CLK_TOP_MSDCPLL_D2 92 103df0225a4SMars Cheng #define CLK_TOP_MSDCPLL_D4 93 104df0225a4SMars Cheng #define CLK_TOP_MSDCPLL_D8 94 105df0225a4SMars Cheng #define CLK_TOP_NR 95 106df0225a4SMars Cheng 107df0225a4SMars Cheng /* APMIXED_SYS */ 108df0225a4SMars Cheng #define CLK_APMIXED_MAINPLL 1 109df0225a4SMars Cheng #define CLK_APMIXED_UNIVPLL 2 110df0225a4SMars Cheng #define CLK_APMIXED_MFGPLL 3 111df0225a4SMars Cheng #define CLK_APMIXED_MSDCPLL 4 112df0225a4SMars Cheng #define CLK_APMIXED_IMGPLL 5 113df0225a4SMars Cheng #define CLK_APMIXED_TVDPLL 6 114df0225a4SMars Cheng #define CLK_APMIXED_CODECPLL 7 115df0225a4SMars Cheng #define CLK_APMIXED_VDECPLL 8 116df0225a4SMars Cheng #define CLK_APMIXED_APLL1 9 117df0225a4SMars Cheng #define CLK_APMIXED_APLL2 10 118df0225a4SMars Cheng #define CLK_APMIXED_NR 11 119df0225a4SMars Cheng 120df0225a4SMars Cheng /* INFRA_SYS */ 121df0225a4SMars Cheng #define CLK_INFRA_PMIC_TMR 1 122df0225a4SMars Cheng #define CLK_INFRA_PMIC_AP 2 123df0225a4SMars Cheng #define CLK_INFRA_PMIC_MD 3 124df0225a4SMars Cheng #define CLK_INFRA_PMIC_CONN 4 125df0225a4SMars Cheng #define CLK_INFRA_SCP 5 126df0225a4SMars Cheng #define CLK_INFRA_SEJ 6 127df0225a4SMars Cheng #define CLK_INFRA_APXGPT 7 128df0225a4SMars Cheng #define CLK_INFRA_SEJ_13M 8 129df0225a4SMars Cheng #define CLK_INFRA_ICUSB 9 130df0225a4SMars Cheng #define CLK_INFRA_GCE 10 131df0225a4SMars Cheng #define CLK_INFRA_THERM 11 132df0225a4SMars Cheng #define CLK_INFRA_I2C0 12 133df0225a4SMars Cheng #define CLK_INFRA_I2C1 13 134df0225a4SMars Cheng #define CLK_INFRA_I2C2 14 135df0225a4SMars Cheng #define CLK_INFRA_I2C3 15 136df0225a4SMars Cheng #define CLK_INFRA_PWM_HCLK 16 137df0225a4SMars Cheng #define CLK_INFRA_PWM1 17 138df0225a4SMars Cheng #define CLK_INFRA_PWM2 18 139df0225a4SMars Cheng #define CLK_INFRA_PWM3 19 140df0225a4SMars Cheng #define CLK_INFRA_PWM4 20 141df0225a4SMars Cheng #define CLK_INFRA_PWM 21 142df0225a4SMars Cheng #define CLK_INFRA_UART0 22 143df0225a4SMars Cheng #define CLK_INFRA_UART1 23 144df0225a4SMars Cheng #define CLK_INFRA_UART2 24 145df0225a4SMars Cheng #define CLK_INFRA_UART3 25 146df0225a4SMars Cheng #define CLK_INFRA_MD2MD_CCIF_0 26 147df0225a4SMars Cheng #define CLK_INFRA_MD2MD_CCIF_1 27 148df0225a4SMars Cheng #define CLK_INFRA_MD2MD_CCIF_2 28 149df0225a4SMars Cheng #define CLK_INFRA_FHCTL 29 150df0225a4SMars Cheng #define CLK_INFRA_BTIF 30 151df0225a4SMars Cheng #define CLK_INFRA_MD2MD_CCIF_3 31 152df0225a4SMars Cheng #define CLK_INFRA_SPI 32 153df0225a4SMars Cheng #define CLK_INFRA_MSDC0 33 154df0225a4SMars Cheng #define CLK_INFRA_MD2MD_CCIF_4 34 155df0225a4SMars Cheng #define CLK_INFRA_MSDC1 35 156df0225a4SMars Cheng #define CLK_INFRA_MSDC2 36 157df0225a4SMars Cheng #define CLK_INFRA_MD2MD_CCIF_5 37 158df0225a4SMars Cheng #define CLK_INFRA_GCPU 38 159df0225a4SMars Cheng #define CLK_INFRA_TRNG 39 160df0225a4SMars Cheng #define CLK_INFRA_AUXADC 40 161df0225a4SMars Cheng #define CLK_INFRA_CPUM 41 162df0225a4SMars Cheng #define CLK_INFRA_AP_C2K_CCIF_0 42 163df0225a4SMars Cheng #define CLK_INFRA_AP_C2K_CCIF_1 43 164df0225a4SMars Cheng #define CLK_INFRA_CLDMA 44 165df0225a4SMars Cheng #define CLK_INFRA_DISP_PWM 45 166df0225a4SMars Cheng #define CLK_INFRA_AP_DMA 46 167df0225a4SMars Cheng #define CLK_INFRA_DEVICE_APC 47 168df0225a4SMars Cheng #define CLK_INFRA_L2C_SRAM 48 169df0225a4SMars Cheng #define CLK_INFRA_CCIF_AP 49 170df0225a4SMars Cheng #define CLK_INFRA_AUDIO 50 171df0225a4SMars Cheng #define CLK_INFRA_CCIF_MD 51 172df0225a4SMars Cheng #define CLK_INFRA_DRAMC_F26M 52 173df0225a4SMars Cheng #define CLK_INFRA_I2C4 53 174df0225a4SMars Cheng #define CLK_INFRA_I2C_APPM 54 175df0225a4SMars Cheng #define CLK_INFRA_I2C_GPUPM 55 176df0225a4SMars Cheng #define CLK_INFRA_I2C2_IMM 56 177df0225a4SMars Cheng #define CLK_INFRA_I2C2_ARB 57 178df0225a4SMars Cheng #define CLK_INFRA_I2C3_IMM 58 179df0225a4SMars Cheng #define CLK_INFRA_I2C3_ARB 59 180df0225a4SMars Cheng #define CLK_INFRA_I2C5 60 181df0225a4SMars Cheng #define CLK_INFRA_SYS_CIRQ 61 182df0225a4SMars Cheng #define CLK_INFRA_SPI1 62 183df0225a4SMars Cheng #define CLK_INFRA_DRAMC_B_F26M 63 184df0225a4SMars Cheng #define CLK_INFRA_ANC_MD32 64 185df0225a4SMars Cheng #define CLK_INFRA_ANC_MD32_32K 65 186df0225a4SMars Cheng #define CLK_INFRA_DVFS_SPM1 66 187df0225a4SMars Cheng #define CLK_INFRA_AES_TOP0 67 188df0225a4SMars Cheng #define CLK_INFRA_AES_TOP1 68 189df0225a4SMars Cheng #define CLK_INFRA_SSUSB_BUS 69 190df0225a4SMars Cheng #define CLK_INFRA_SPI2 70 191df0225a4SMars Cheng #define CLK_INFRA_SPI3 71 192df0225a4SMars Cheng #define CLK_INFRA_SPI4 72 193df0225a4SMars Cheng #define CLK_INFRA_SPI5 73 194df0225a4SMars Cheng #define CLK_INFRA_IRTX 74 195df0225a4SMars Cheng #define CLK_INFRA_SSUSB_SYS 75 196df0225a4SMars Cheng #define CLK_INFRA_SSUSB_REF 76 197df0225a4SMars Cheng #define CLK_INFRA_AUDIO_26M 77 198df0225a4SMars Cheng #define CLK_INFRA_AUDIO_26M_PAD_TOP 78 199df0225a4SMars Cheng #define CLK_INFRA_MODEM_TEMP_SHARE 79 200df0225a4SMars Cheng #define CLK_INFRA_VAD_WRAP_SOC 80 201df0225a4SMars Cheng #define CLK_INFRA_DRAMC_CONF 81 202df0225a4SMars Cheng #define CLK_INFRA_DRAMC_B_CONF 82 203df0225a4SMars Cheng #define CLK_INFRA_MFG_VCG 83 204df0225a4SMars Cheng #define CLK_INFRA_13M 84 205df0225a4SMars Cheng #define CLK_INFRA_NR 85 206df0225a4SMars Cheng 207df0225a4SMars Cheng /* IMG_SYS */ 208df0225a4SMars Cheng #define CLK_IMG_FDVT 1 209df0225a4SMars Cheng #define CLK_IMG_DPE 2 210df0225a4SMars Cheng #define CLK_IMG_DIP 3 211df0225a4SMars Cheng #define CLK_IMG_LARB6 4 212df0225a4SMars Cheng #define CLK_IMG_NR 5 213df0225a4SMars Cheng 214df0225a4SMars Cheng /* MM_SYS */ 215df0225a4SMars Cheng #define CLK_MM_SMI_COMMON 1 216df0225a4SMars Cheng #define CLK_MM_SMI_LARB0 2 217df0225a4SMars Cheng #define CLK_MM_SMI_LARB5 3 218df0225a4SMars Cheng #define CLK_MM_CAM_MDP 4 219df0225a4SMars Cheng #define CLK_MM_MDP_RDMA0 5 220df0225a4SMars Cheng #define CLK_MM_MDP_RDMA1 6 221df0225a4SMars Cheng #define CLK_MM_MDP_RSZ0 7 222df0225a4SMars Cheng #define CLK_MM_MDP_RSZ1 8 223df0225a4SMars Cheng #define CLK_MM_MDP_RSZ2 9 224df0225a4SMars Cheng #define CLK_MM_MDP_TDSHP 10 225df0225a4SMars Cheng #define CLK_MM_MDP_COLOR 11 226df0225a4SMars Cheng #define CLK_MM_MDP_WDMA 12 227df0225a4SMars Cheng #define CLK_MM_MDP_WROT0 13 228df0225a4SMars Cheng #define CLK_MM_MDP_WROT1 14 229df0225a4SMars Cheng #define CLK_MM_FAKE_ENG 15 230df0225a4SMars Cheng #define CLK_MM_DISP_OVL0 16 231df0225a4SMars Cheng #define CLK_MM_DISP_OVL1 17 232df0225a4SMars Cheng #define CLK_MM_DISP_OVL0_2L 18 233df0225a4SMars Cheng #define CLK_MM_DISP_OVL1_2L 19 234df0225a4SMars Cheng #define CLK_MM_DISP_RDMA0 20 235df0225a4SMars Cheng #define CLK_MM_DISP_RDMA1 21 236df0225a4SMars Cheng #define CLK_MM_DISP_WDMA0 22 237df0225a4SMars Cheng #define CLK_MM_DISP_WDMA1 23 238df0225a4SMars Cheng #define CLK_MM_DISP_COLOR 24 239df0225a4SMars Cheng #define CLK_MM_DISP_CCORR 25 240df0225a4SMars Cheng #define CLK_MM_DISP_AAL 26 241df0225a4SMars Cheng #define CLK_MM_DISP_GAMMA 27 242df0225a4SMars Cheng #define CLK_MM_DISP_OD 28 243df0225a4SMars Cheng #define CLK_MM_DISP_DITHER 29 244df0225a4SMars Cheng #define CLK_MM_DISP_UFOE 30 245df0225a4SMars Cheng #define CLK_MM_DISP_DSC 31 246df0225a4SMars Cheng #define CLK_MM_DISP_SPLIT 32 247df0225a4SMars Cheng #define CLK_MM_DSI0_MM_CLOCK 33 248df0225a4SMars Cheng #define CLK_MM_DSI1_MM_CLOCK 34 249df0225a4SMars Cheng #define CLK_MM_DPI_MM_CLOCK 35 250df0225a4SMars Cheng #define CLK_MM_DPI_INTERFACE_CLOCK 36 251df0225a4SMars Cheng #define CLK_MM_LARB4_AXI_ASIF_MM_CLOCK 37 252df0225a4SMars Cheng #define CLK_MM_LARB4_AXI_ASIF_MJC_CLOCK 38 253df0225a4SMars Cheng #define CLK_MM_DISP_OVL0_MOUT_CLOCK 39 254df0225a4SMars Cheng #define CLK_MM_FAKE_ENG2 40 255df0225a4SMars Cheng #define CLK_MM_DSI0_INTERFACE_CLOCK 41 256df0225a4SMars Cheng #define CLK_MM_DSI1_INTERFACE_CLOCK 42 257df0225a4SMars Cheng #define CLK_MM_NR 43 258df0225a4SMars Cheng 259df0225a4SMars Cheng /* VDEC_SYS */ 260df0225a4SMars Cheng #define CLK_VDEC_CKEN_ENG 1 261df0225a4SMars Cheng #define CLK_VDEC_ACTIVE 2 262df0225a4SMars Cheng #define CLK_VDEC_CKEN 3 263df0225a4SMars Cheng #define CLK_VDEC_LARB1_CKEN 4 264df0225a4SMars Cheng #define CLK_VDEC_NR 5 265df0225a4SMars Cheng 266df0225a4SMars Cheng /* VENC_SYS */ 267df0225a4SMars Cheng #define CLK_VENC_0 1 268df0225a4SMars Cheng #define CLK_VENC_1 2 269df0225a4SMars Cheng #define CLK_VENC_2 3 270df0225a4SMars Cheng #define CLK_VENC_3 4 271df0225a4SMars Cheng #define CLK_VENC_NR 5 272df0225a4SMars Cheng 273df0225a4SMars Cheng #endif /* _DT_BINDINGS_CLK_MT6797_H */ 274