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Searched refs:CLAMP_IO (Results 1 – 25 of 27) sorted by relevance

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/linux/drivers/clk/qcom/
H A Dgdsc.h63 #define CLAMP_IO BIT(1) macro
H A Dgpucc-sdm845.c138 .flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR,
H A Dgpucc-sc7180.c177 .flags = CLAMP_IO,
H A Dgpucc-sm8250.c248 .flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR,
H A Dgpucc-sm8150.c240 .flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR,
H A Dgpucc-sdm660.c253 .flags = CLAMP_IO | SW_RESET | AON_RESET | NO_RET_PERIPH,
H A Dgdsc.c299 if (sc->flags & CLAMP_IO) { in gdsc_enable()
386 if (sc->flags & CLAMP_IO) in gdsc_disable()
H A Dgpucc-msm8998.c269 .flags = CLAMP_IO | SW_RESET | AON_RESET | NO_RET_PERIPH,
H A Dgpucc-qcm2290.c320 .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR | CLAMP_IO | AON_RESET | SW_RESET,
H A Dgpucc-sc8280xp.c401 .flags = CLAMP_IO | RETAIN_FF_ENABLE,
H A Dgpucc-sm6375.c379 .flags = CLAMP_IO | SW_RESET | AON_RESET,
H A Dgpucc-sar2130p.c416 .flags = CLAMP_IO | AON_RESET | SW_RESET,
H A Dgpucc-sc7280.c405 .flags = CLAMP_IO | RETAIN_FF_ENABLE,
H A Dgpucc-sm6115.c416 .flags = CLAMP_IO | SW_RESET | VOTABLE,
H A Dgpu2cc-nord.c444 .flags = CLAMP_IO | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
H A Dgpucc-sm6350.c436 .flags = CLAMP_IO | POLL_CFG_GDSCR,
H A Dgpucc-x1p42100.c473 .flags = CLAMP_IO | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
H A Dgpucc-nord.c491 .flags = CLAMP_IO | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
H A Dgpucc-sm8550.c499 .flags = CLAMP_IO | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
H A Dgpucc-sm8350.c527 .flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR,
H A Dgpucc-x1e80100.c556 .flags = CLAMP_IO | AON_RESET | SW_RESET | POLL_CFG_GDSCR,
H A Dgpucc-sm8650.c564 .flags = CLAMP_IO | AON_RESET | SW_RESET | POLL_CFG_GDSCR,
H A Dgpucc-sm4450.c693 .flags = CLAMP_IO | AON_RESET | SW_RESET | POLL_CFG_GDSCR,
H A Dgpucc-sm8450.c691 .flags = CLAMP_IO | AON_RESET | SW_RESET | POLL_CFG_GDSCR,
H A Dmmcc-msm8994.c2379 .flags = CLAMP_IO,

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