1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
4 */
5
6 #include <linux/clk-provider.h>
7 #include <linux/module.h>
8 #include <linux/platform_device.h>
9 #include <linux/regmap.h>
10
11 #include <dt-bindings/clock/qcom,nord-gpucc.h>
12
13 #include "clk-alpha-pll.h"
14 #include "clk-branch.h"
15 #include "clk-pll.h"
16 #include "clk-rcg.h"
17 #include "clk-regmap.h"
18 #include "clk-regmap-divider.h"
19 #include "clk-regmap-mux.h"
20 #include "common.h"
21 #include "gdsc.h"
22 #include "reset.h"
23
24 enum {
25 DT_BI_TCXO,
26 DT_GPLL0_OUT_MAIN,
27 DT_GPLL0_OUT_MAIN_DIV,
28 };
29
30 enum {
31 P_BI_TCXO,
32 P_GPLL0_OUT_MAIN,
33 P_GPLL0_OUT_MAIN_DIV,
34 P_GPU_CC_PLL0_OUT_MAIN,
35 P_GPU_CC_PLL1_OUT_MAIN,
36 };
37
38 static const struct pll_vco lucid_ole_vco[] = {
39 { 249600000, 2300000000, 0 },
40 };
41
42 /* 936.0 MHz Configuration */
43 static const struct alpha_pll_config gpu_cc_pll0_config = {
44 .l = 0x30,
45 .alpha = 0xc000,
46 .config_ctl_val = 0x20485699,
47 .config_ctl_hi_val = 0x00182261,
48 .config_ctl_hi1_val = 0x82aa299c,
49 .test_ctl_val = 0x00000000,
50 .test_ctl_hi_val = 0x00000003,
51 .test_ctl_hi1_val = 0x00009000,
52 .test_ctl_hi2_val = 0x00000034,
53 .user_ctl_val = 0x00000000,
54 .user_ctl_hi_val = 0x00400005,
55 };
56
57 static struct clk_alpha_pll gpu_cc_pll0 = {
58 .offset = 0x0,
59 .config = &gpu_cc_pll0_config,
60 .vco_table = lucid_ole_vco,
61 .num_vco = ARRAY_SIZE(lucid_ole_vco),
62 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
63 .clkr = {
64 .hw.init = &(const struct clk_init_data) {
65 .name = "gpu_cc_pll0",
66 .parent_data = &(const struct clk_parent_data) {
67 .index = DT_BI_TCXO,
68 },
69 .num_parents = 1,
70 .ops = &clk_alpha_pll_lucid_evo_ops,
71 },
72 },
73 };
74
75 /* 1250.0 MHz Configuration */
76 static const struct alpha_pll_config gpu_cc_pll1_config = {
77 .l = 0x41,
78 .alpha = 0x1aaa,
79 .config_ctl_val = 0x20485699,
80 .config_ctl_hi_val = 0x00182261,
81 .config_ctl_hi1_val = 0x82aa299c,
82 .test_ctl_val = 0x00000000,
83 .test_ctl_hi_val = 0x00000003,
84 .test_ctl_hi1_val = 0x00009000,
85 .test_ctl_hi2_val = 0x00000034,
86 .user_ctl_val = 0x00000000,
87 .user_ctl_hi_val = 0x00400005,
88 };
89
90 static struct clk_alpha_pll gpu_cc_pll1 = {
91 .offset = 0x1000,
92 .config = &gpu_cc_pll1_config,
93 .vco_table = lucid_ole_vco,
94 .num_vco = ARRAY_SIZE(lucid_ole_vco),
95 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
96 .clkr = {
97 .hw.init = &(const struct clk_init_data) {
98 .name = "gpu_cc_pll1",
99 .parent_data = &(const struct clk_parent_data) {
100 .index = DT_BI_TCXO,
101 },
102 .num_parents = 1,
103 .ops = &clk_alpha_pll_lucid_evo_ops,
104 },
105 },
106 };
107
108 static const struct parent_map gpu_cc_parent_map_0[] = {
109 { P_BI_TCXO, 0 },
110 { P_GPLL0_OUT_MAIN, 5 },
111 { P_GPLL0_OUT_MAIN_DIV, 6 },
112 };
113
114 static const struct clk_parent_data gpu_cc_parent_data_0[] = {
115 { .index = DT_BI_TCXO },
116 { .index = DT_GPLL0_OUT_MAIN },
117 { .index = DT_GPLL0_OUT_MAIN_DIV },
118 };
119
120 static const struct parent_map gpu_cc_parent_map_1[] = {
121 { P_BI_TCXO, 0 },
122 { P_GPU_CC_PLL0_OUT_MAIN, 1 },
123 { P_GPU_CC_PLL1_OUT_MAIN, 3 },
124 { P_GPLL0_OUT_MAIN, 5 },
125 { P_GPLL0_OUT_MAIN_DIV, 6 },
126 };
127
128 static const struct clk_parent_data gpu_cc_parent_data_1[] = {
129 { .index = DT_BI_TCXO },
130 { .hw = &gpu_cc_pll0.clkr.hw },
131 { .hw = &gpu_cc_pll1.clkr.hw },
132 { .index = DT_GPLL0_OUT_MAIN },
133 { .index = DT_GPLL0_OUT_MAIN_DIV },
134 };
135
136 static const struct parent_map gpu_cc_parent_map_2[] = {
137 { P_BI_TCXO, 0 },
138 { P_GPU_CC_PLL1_OUT_MAIN, 3 },
139 { P_GPLL0_OUT_MAIN, 5 },
140 { P_GPLL0_OUT_MAIN_DIV, 6 },
141 };
142
143 static const struct clk_parent_data gpu_cc_parent_data_2[] = {
144 { .index = DT_BI_TCXO },
145 { .hw = &gpu_cc_pll1.clkr.hw },
146 { .index = DT_GPLL0_OUT_MAIN },
147 { .index = DT_GPLL0_OUT_MAIN_DIV },
148 };
149
150 static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = {
151 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
152 { }
153 };
154
155 static struct clk_rcg2 gpu_cc_ff_clk_src = {
156 .cmd_rcgr = 0x93d4,
157 .mnd_width = 0,
158 .hid_width = 5,
159 .parent_map = gpu_cc_parent_map_0,
160 .freq_tbl = ftbl_gpu_cc_ff_clk_src,
161 .hw_clk_ctrl = true,
162 .clkr.hw.init = &(const struct clk_init_data) {
163 .name = "gpu_cc_ff_clk_src",
164 .parent_data = gpu_cc_parent_data_0,
165 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
166 .flags = CLK_SET_RATE_PARENT,
167 .ops = &clk_rcg2_shared_ops,
168 },
169 };
170
171 static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
172 F(416666667, P_GPU_CC_PLL1_OUT_MAIN, 3, 0, 0),
173 F(625000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0),
174 { }
175 };
176
177 static struct clk_rcg2 gpu_cc_gmu_clk_src = {
178 .cmd_rcgr = 0x92b8,
179 .mnd_width = 0,
180 .hid_width = 5,
181 .parent_map = gpu_cc_parent_map_1,
182 .freq_tbl = ftbl_gpu_cc_gmu_clk_src,
183 .hw_clk_ctrl = true,
184 .clkr.hw.init = &(const struct clk_init_data) {
185 .name = "gpu_cc_gmu_clk_src",
186 .parent_data = gpu_cc_parent_data_1,
187 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
188 .flags = CLK_SET_RATE_PARENT,
189 .ops = &clk_rcg2_shared_ops,
190 },
191 };
192
193 static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = {
194 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
195 { }
196 };
197
198 static struct clk_rcg2 gpu_cc_hub_clk_src = {
199 .cmd_rcgr = 0x938c,
200 .mnd_width = 0,
201 .hid_width = 5,
202 .parent_map = gpu_cc_parent_map_2,
203 .freq_tbl = ftbl_gpu_cc_hub_clk_src,
204 .hw_clk_ctrl = true,
205 .clkr.hw.init = &(const struct clk_init_data) {
206 .name = "gpu_cc_hub_clk_src",
207 .parent_data = gpu_cc_parent_data_2,
208 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_2),
209 .flags = CLK_SET_RATE_PARENT,
210 .ops = &clk_rcg2_shared_ops,
211 },
212 };
213
214 static struct clk_regmap_div gpu_cc_hub_div_clk_src = {
215 .reg = 0x93cc,
216 .shift = 0,
217 .width = 4,
218 .clkr.hw.init = &(const struct clk_init_data) {
219 .name = "gpu_cc_hub_div_clk_src",
220 .parent_hws = (const struct clk_hw*[]) {
221 &gpu_cc_hub_clk_src.clkr.hw,
222 },
223 .num_parents = 1,
224 .flags = CLK_SET_RATE_PARENT,
225 .ops = &clk_regmap_div_ro_ops,
226 },
227 };
228
229 static struct clk_branch gpu_cc_acd_gfx3d_clk = {
230 .halt_reg = 0x92a8,
231 .halt_check = BRANCH_HALT,
232 .clkr = {
233 .enable_reg = 0x92a8,
234 .enable_mask = BIT(0),
235 .hw.init = &(const struct clk_init_data) {
236 .name = "gpu_cc_acd_gfx3d_clk",
237 .ops = &clk_branch2_ops,
238 },
239 },
240 };
241
242 static struct clk_branch gpu_cc_acmu_clk = {
243 .halt_reg = 0x9294,
244 .halt_check = BRANCH_HALT,
245 .clkr = {
246 .enable_reg = 0x9294,
247 .enable_mask = BIT(0),
248 .hw.init = &(const struct clk_init_data) {
249 .name = "gpu_cc_acmu_clk",
250 .ops = &clk_branch2_ops,
251 },
252 },
253 };
254
255 static struct clk_branch gpu_cc_ahb_clk = {
256 .halt_reg = 0x9150,
257 .halt_check = BRANCH_HALT_DELAY,
258 .clkr = {
259 .enable_reg = 0x9150,
260 .enable_mask = BIT(0),
261 .hw.init = &(const struct clk_init_data) {
262 .name = "gpu_cc_ahb_clk",
263 .parent_hws = (const struct clk_hw*[]) {
264 &gpu_cc_hub_div_clk_src.clkr.hw,
265 },
266 .num_parents = 1,
267 .flags = CLK_SET_RATE_PARENT,
268 .ops = &clk_branch2_ops,
269 },
270 },
271 };
272
273 static struct clk_branch gpu_cc_crc_ahb_clk = {
274 .halt_reg = 0x9154,
275 .halt_check = BRANCH_HALT_VOTED,
276 .clkr = {
277 .enable_reg = 0x9154,
278 .enable_mask = BIT(0),
279 .hw.init = &(const struct clk_init_data) {
280 .name = "gpu_cc_crc_ahb_clk",
281 .parent_hws = (const struct clk_hw*[]) {
282 &gpu_cc_hub_div_clk_src.clkr.hw,
283 },
284 .num_parents = 1,
285 .flags = CLK_SET_RATE_PARENT,
286 .ops = &clk_branch2_ops,
287 },
288 },
289 };
290
291 static struct clk_branch gpu_cc_cx_accu_shift_clk = {
292 .halt_reg = 0x91a4,
293 .halt_check = BRANCH_HALT_VOTED,
294 .clkr = {
295 .enable_reg = 0x91a4,
296 .enable_mask = BIT(0),
297 .hw.init = &(const struct clk_init_data) {
298 .name = "gpu_cc_cx_accu_shift_clk",
299 .ops = &clk_branch2_ops,
300 },
301 },
302 };
303
304 static struct clk_branch gpu_cc_cx_ff_clk = {
305 .halt_reg = 0x9184,
306 .halt_check = BRANCH_HALT,
307 .clkr = {
308 .enable_reg = 0x9184,
309 .enable_mask = BIT(0),
310 .hw.init = &(const struct clk_init_data) {
311 .name = "gpu_cc_cx_ff_clk",
312 .parent_hws = (const struct clk_hw*[]) {
313 &gpu_cc_ff_clk_src.clkr.hw,
314 },
315 .num_parents = 1,
316 .flags = CLK_SET_RATE_PARENT,
317 .ops = &clk_branch2_ops,
318 },
319 },
320 };
321
322 static struct clk_branch gpu_cc_cx_gmu_clk = {
323 .halt_reg = 0x916c,
324 .halt_check = BRANCH_HALT_VOTED,
325 .clkr = {
326 .enable_reg = 0x916c,
327 .enable_mask = BIT(0),
328 .hw.init = &(const struct clk_init_data) {
329 .name = "gpu_cc_cx_gmu_clk",
330 .parent_hws = (const struct clk_hw*[]) {
331 &gpu_cc_gmu_clk_src.clkr.hw,
332 },
333 .num_parents = 1,
334 .flags = CLK_SET_RATE_PARENT,
335 .ops = &clk_branch2_aon_ops,
336 },
337 },
338 };
339
340 static struct clk_branch gpu_cc_cxo_clk = {
341 .halt_reg = 0x917c,
342 .halt_check = BRANCH_HALT,
343 .clkr = {
344 .enable_reg = 0x917c,
345 .enable_mask = BIT(0),
346 .hw.init = &(const struct clk_init_data) {
347 .name = "gpu_cc_cxo_clk",
348 .ops = &clk_branch2_ops,
349 },
350 },
351 };
352
353 static struct clk_branch gpu_cc_dpm_clk = {
354 .halt_reg = 0x91a8,
355 .halt_check = BRANCH_HALT,
356 .clkr = {
357 .enable_reg = 0x91a8,
358 .enable_mask = BIT(0),
359 .hw.init = &(const struct clk_init_data) {
360 .name = "gpu_cc_dpm_clk",
361 .ops = &clk_branch2_ops,
362 },
363 },
364 };
365
366 static struct clk_branch gpu_cc_freq_measure_clk = {
367 .halt_reg = 0x9008,
368 .halt_check = BRANCH_HALT,
369 .clkr = {
370 .enable_reg = 0x9008,
371 .enable_mask = BIT(0),
372 .hw.init = &(const struct clk_init_data) {
373 .name = "gpu_cc_freq_measure_clk",
374 .ops = &clk_branch2_ops,
375 },
376 },
377 };
378
379 static struct clk_branch gpu_cc_gpu_smmu_vote_clk = {
380 .halt_reg = 0x7000,
381 .halt_check = BRANCH_HALT_VOTED,
382 .clkr = {
383 .enable_reg = 0x7000,
384 .enable_mask = BIT(0),
385 .hw.init = &(const struct clk_init_data) {
386 .name = "gpu_cc_gpu_smmu_vote_clk",
387 .ops = &clk_branch2_ops,
388 },
389 },
390 };
391
392 static struct clk_branch gpu_cc_hub_aon_clk = {
393 .halt_reg = 0x9388,
394 .halt_check = BRANCH_HALT_VOTED,
395 .clkr = {
396 .enable_reg = 0x9388,
397 .enable_mask = BIT(0),
398 .hw.init = &(const struct clk_init_data) {
399 .name = "gpu_cc_hub_aon_clk",
400 .parent_hws = (const struct clk_hw*[]) {
401 &gpu_cc_hub_clk_src.clkr.hw,
402 },
403 .num_parents = 1,
404 .flags = CLK_SET_RATE_PARENT,
405 .ops = &clk_branch2_aon_ops,
406 },
407 },
408 };
409
410 static struct clk_branch gpu_cc_hub_cx_int_clk = {
411 .halt_reg = 0x9180,
412 .halt_check = BRANCH_HALT_VOTED,
413 .clkr = {
414 .enable_reg = 0x9180,
415 .enable_mask = BIT(0),
416 .hw.init = &(const struct clk_init_data) {
417 .name = "gpu_cc_hub_cx_int_clk",
418 .parent_hws = (const struct clk_hw*[]) {
419 &gpu_cc_hub_clk_src.clkr.hw,
420 },
421 .num_parents = 1,
422 .flags = CLK_SET_RATE_PARENT,
423 .ops = &clk_branch2_aon_ops,
424 },
425 },
426 };
427
428 static struct clk_branch gpu_cc_memnoc_gfx_clk = {
429 .halt_reg = 0x9188,
430 .halt_check = BRANCH_HALT_VOTED,
431 .clkr = {
432 .enable_reg = 0x9188,
433 .enable_mask = BIT(0),
434 .hw.init = &(const struct clk_init_data) {
435 .name = "gpu_cc_memnoc_gfx_clk",
436 .ops = &clk_branch2_ops,
437 },
438 },
439 };
440
441 static struct clk_branch gpu_cc_mnd1x_gfx3d_clk = {
442 .halt_reg = 0x92ac,
443 .halt_check = BRANCH_HALT,
444 .clkr = {
445 .enable_reg = 0x92ac,
446 .enable_mask = BIT(0),
447 .hw.init = &(const struct clk_init_data) {
448 .name = "gpu_cc_mnd1x_gfx3d_clk",
449 .ops = &clk_branch2_ops,
450 },
451 },
452 };
453
454 static struct clk_branch gpu_cc_sleep_clk = {
455 .halt_reg = 0x9164,
456 .halt_check = BRANCH_HALT_VOTED,
457 .clkr = {
458 .enable_reg = 0x9164,
459 .enable_mask = BIT(0),
460 .hw.init = &(const struct clk_init_data) {
461 .name = "gpu_cc_sleep_clk",
462 .ops = &clk_branch2_ops,
463 },
464 },
465 };
466
467 static struct gdsc gpu_cc_cx_gdsc = {
468 .gdscr = 0x90e8,
469 .gds_hw_ctrl = 0x9128,
470 .en_rest_wait_val = 0x2,
471 .en_few_wait_val = 0x2,
472 .clk_dis_wait_val = 0xf,
473 .pd = {
474 .name = "gpu_cc_cx_gdsc",
475 },
476 .pwrsts = PWRSTS_OFF_ON,
477 .flags = VOTABLE | RETAIN_FF_ENABLE,
478 };
479
480 static struct gdsc gpu_cc_gx_gdsc = {
481 .gdscr = 0x905c,
482 .clamp_io_ctrl = 0x9504,
483 .en_rest_wait_val = 0x2,
484 .en_few_wait_val = 0x2,
485 .clk_dis_wait_val = 0xf,
486 .pd = {
487 .name = "gpu_cc_gx_gdsc",
488 .power_on = gdsc_gx_do_nothing_enable,
489 },
490 .pwrsts = PWRSTS_OFF_ON,
491 .flags = CLAMP_IO | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
492 };
493
494 static struct clk_regmap *gpu_cc_nord_clocks[] = {
495 [GPU_CC_ACD_GFX3D_CLK] = &gpu_cc_acd_gfx3d_clk.clkr,
496 [GPU_CC_ACMU_CLK] = &gpu_cc_acmu_clk.clkr,
497 [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
498 [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
499 [GPU_CC_CX_ACCU_SHIFT_CLK] = &gpu_cc_cx_accu_shift_clk.clkr,
500 [GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr,
501 [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
502 [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
503 [GPU_CC_DPM_CLK] = &gpu_cc_dpm_clk.clkr,
504 [GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr,
505 [GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr,
506 [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
507 [GPU_CC_GPU_SMMU_VOTE_CLK] = &gpu_cc_gpu_smmu_vote_clk.clkr,
508 [GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr,
509 [GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr,
510 [GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr,
511 [GPU_CC_HUB_DIV_CLK_SRC] = &gpu_cc_hub_div_clk_src.clkr,
512 [GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr,
513 [GPU_CC_MND1X_GFX3D_CLK] = &gpu_cc_mnd1x_gfx3d_clk.clkr,
514 [GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
515 [GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
516 [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
517 };
518
519 static struct gdsc *gpu_cc_nord_gdscs[] = {
520 [GPU_CC_CX_GDSC] = &gpu_cc_cx_gdsc,
521 [GPU_CC_GX_GDSC] = &gpu_cc_gx_gdsc,
522 };
523
524 static const struct qcom_reset_map gpu_cc_nord_resets[] = {
525 [GPU_CC_ACD_BCR] = { 0x92f8 },
526 [GPU_CC_CB_BCR] = { 0x9340 },
527 [GPU_CC_CX_BCR] = { 0x90e4 },
528 [GPU_CC_FAST_HUB_BCR] = { 0x9384 },
529 [GPU_CC_GFX3D_AON_BCR] = { 0x91ac },
530 [GPU_CC_GX_BCR] = { 0x9058 },
531 [GPU_CC_XO_BCR] = { 0x9000 },
532 };
533
534 static struct clk_alpha_pll *gpu_cc_nord_plls[] = {
535 &gpu_cc_pll0,
536 &gpu_cc_pll1,
537 };
538
539 static const u32 gpu_cc_nord_critical_cbcrs[] = {
540 0x9004, /* GPU_CC_CXO_AON_CLK */
541 0x900c, /* GPU_CC_DEMET_CLK */
542 };
543
544 static const struct regmap_config gpu_cc_nord_regmap_config = {
545 .reg_bits = 32,
546 .reg_stride = 4,
547 .val_bits = 32,
548 .max_register = 0x9660,
549 .fast_io = true,
550 };
551
552 static const struct qcom_cc_driver_data gpu_cc_nord_driver_data = {
553 .alpha_plls = gpu_cc_nord_plls,
554 .num_alpha_plls = ARRAY_SIZE(gpu_cc_nord_plls),
555 .clk_cbcrs = gpu_cc_nord_critical_cbcrs,
556 .num_clk_cbcrs = ARRAY_SIZE(gpu_cc_nord_critical_cbcrs),
557 };
558
559 static const struct qcom_cc_desc gpu_cc_nord_desc = {
560 .config = &gpu_cc_nord_regmap_config,
561 .clks = gpu_cc_nord_clocks,
562 .num_clks = ARRAY_SIZE(gpu_cc_nord_clocks),
563 .resets = gpu_cc_nord_resets,
564 .num_resets = ARRAY_SIZE(gpu_cc_nord_resets),
565 .gdscs = gpu_cc_nord_gdscs,
566 .num_gdscs = ARRAY_SIZE(gpu_cc_nord_gdscs),
567 .use_rpm = true,
568 .driver_data = &gpu_cc_nord_driver_data,
569 };
570
571 static const struct of_device_id gpu_cc_nord_match_table[] = {
572 { .compatible = "qcom,nord-gpucc" },
573 { }
574 };
575 MODULE_DEVICE_TABLE(of, gpu_cc_nord_match_table);
576
gpu_cc_nord_probe(struct platform_device * pdev)577 static int gpu_cc_nord_probe(struct platform_device *pdev)
578 {
579 return qcom_cc_probe(pdev, &gpu_cc_nord_desc);
580 }
581
582 static struct platform_driver gpu_cc_nord_driver = {
583 .probe = gpu_cc_nord_probe,
584 .driver = {
585 .name = "gpucc-nord",
586 .of_match_table = gpu_cc_nord_match_table,
587 },
588 };
589
590 module_platform_driver(gpu_cc_nord_driver);
591
592 MODULE_DESCRIPTION("QTI GPUCC Nord Driver");
593 MODULE_LICENSE("GPL");
594