1453361cdSAmit Nischal // SPDX-License-Identifier: GPL-2.0
2453361cdSAmit Nischal /*
3453361cdSAmit Nischal * Copyright (c) 2018, The Linux Foundation. All rights reserved.
4453361cdSAmit Nischal */
5453361cdSAmit Nischal
6453361cdSAmit Nischal #include <linux/clk-provider.h>
7453361cdSAmit Nischal #include <linux/module.h>
8453361cdSAmit Nischal #include <linux/platform_device.h>
9453361cdSAmit Nischal #include <linux/regmap.h>
10453361cdSAmit Nischal
11453361cdSAmit Nischal #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
12453361cdSAmit Nischal
13453361cdSAmit Nischal #include "common.h"
14453361cdSAmit Nischal #include "clk-alpha-pll.h"
15453361cdSAmit Nischal #include "clk-branch.h"
16453361cdSAmit Nischal #include "clk-pll.h"
17453361cdSAmit Nischal #include "clk-rcg.h"
18453361cdSAmit Nischal #include "clk-regmap.h"
19453361cdSAmit Nischal #include "gdsc.h"
20453361cdSAmit Nischal
21453361cdSAmit Nischal #define CX_GMU_CBCR_SLEEP_MASK 0xf
22453361cdSAmit Nischal #define CX_GMU_CBCR_SLEEP_SHIFT 4
23453361cdSAmit Nischal #define CX_GMU_CBCR_WAKE_MASK 0xf
24453361cdSAmit Nischal #define CX_GMU_CBCR_WAKE_SHIFT 8
25453361cdSAmit Nischal
26453361cdSAmit Nischal enum {
27453361cdSAmit Nischal P_BI_TCXO,
28453361cdSAmit Nischal P_GPLL0_OUT_MAIN,
29453361cdSAmit Nischal P_GPLL0_OUT_MAIN_DIV,
30453361cdSAmit Nischal P_GPU_CC_PLL1_OUT_MAIN,
31453361cdSAmit Nischal };
32453361cdSAmit Nischal
33453361cdSAmit Nischal static const struct alpha_pll_config gpu_cc_pll1_config = {
34453361cdSAmit Nischal .l = 0x1a,
35453361cdSAmit Nischal .alpha = 0xaab,
36453361cdSAmit Nischal };
37453361cdSAmit Nischal
38453361cdSAmit Nischal static struct clk_alpha_pll gpu_cc_pll1 = {
39453361cdSAmit Nischal .offset = 0x100,
40453361cdSAmit Nischal .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
41453361cdSAmit Nischal .clkr = {
42453361cdSAmit Nischal .hw.init = &(struct clk_init_data){
43453361cdSAmit Nischal .name = "gpu_cc_pll1",
44040184b7SDmitry Baryshkov .parent_data = &(const struct clk_parent_data){
45040184b7SDmitry Baryshkov .fw_name = "bi_tcxo", .name = "bi_tcxo",
46040184b7SDmitry Baryshkov },
47453361cdSAmit Nischal .num_parents = 1,
48453361cdSAmit Nischal .ops = &clk_alpha_pll_fabia_ops,
49453361cdSAmit Nischal },
50453361cdSAmit Nischal },
51453361cdSAmit Nischal };
52453361cdSAmit Nischal
53040184b7SDmitry Baryshkov static const struct parent_map gpu_cc_parent_map_0[] = {
54040184b7SDmitry Baryshkov { P_BI_TCXO, 0 },
55040184b7SDmitry Baryshkov { P_GPU_CC_PLL1_OUT_MAIN, 3 },
56040184b7SDmitry Baryshkov { P_GPLL0_OUT_MAIN, 5 },
57040184b7SDmitry Baryshkov { P_GPLL0_OUT_MAIN_DIV, 6 },
58040184b7SDmitry Baryshkov };
59040184b7SDmitry Baryshkov
60040184b7SDmitry Baryshkov static const struct clk_parent_data gpu_cc_parent_data_0[] = {
61040184b7SDmitry Baryshkov { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
62040184b7SDmitry Baryshkov { .hw = &gpu_cc_pll1.clkr.hw },
63040184b7SDmitry Baryshkov { .fw_name = "gcc_gpu_gpll0_clk_src", .name = "gcc_gpu_gpll0_clk_src" },
64040184b7SDmitry Baryshkov { .fw_name = "gcc_gpu_gpll0_div_clk_src", .name = "gcc_gpu_gpll0_div_clk_src" },
65040184b7SDmitry Baryshkov };
66040184b7SDmitry Baryshkov
67453361cdSAmit Nischal static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
68453361cdSAmit Nischal F(19200000, P_BI_TCXO, 1, 0, 0),
69453361cdSAmit Nischal F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
70453361cdSAmit Nischal F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0),
71453361cdSAmit Nischal { }
72453361cdSAmit Nischal };
73453361cdSAmit Nischal
74453361cdSAmit Nischal static struct clk_rcg2 gpu_cc_gmu_clk_src = {
75453361cdSAmit Nischal .cmd_rcgr = 0x1120,
76453361cdSAmit Nischal .mnd_width = 0,
77453361cdSAmit Nischal .hid_width = 5,
78453361cdSAmit Nischal .parent_map = gpu_cc_parent_map_0,
79453361cdSAmit Nischal .freq_tbl = ftbl_gpu_cc_gmu_clk_src,
80453361cdSAmit Nischal .clkr.hw.init = &(struct clk_init_data){
81453361cdSAmit Nischal .name = "gpu_cc_gmu_clk_src",
82040184b7SDmitry Baryshkov .parent_data = gpu_cc_parent_data_0,
83040184b7SDmitry Baryshkov .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
84453361cdSAmit Nischal .ops = &clk_rcg2_shared_ops,
85453361cdSAmit Nischal },
86453361cdSAmit Nischal };
87453361cdSAmit Nischal
88453361cdSAmit Nischal static struct clk_branch gpu_cc_cx_gmu_clk = {
89453361cdSAmit Nischal .halt_reg = 0x1098,
90453361cdSAmit Nischal .halt_check = BRANCH_HALT,
91453361cdSAmit Nischal .clkr = {
92453361cdSAmit Nischal .enable_reg = 0x1098,
93453361cdSAmit Nischal .enable_mask = BIT(0),
94453361cdSAmit Nischal .hw.init = &(struct clk_init_data){
95453361cdSAmit Nischal .name = "gpu_cc_cx_gmu_clk",
96040184b7SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){
97040184b7SDmitry Baryshkov &gpu_cc_gmu_clk_src.clkr.hw,
98453361cdSAmit Nischal },
99453361cdSAmit Nischal .num_parents = 1,
100453361cdSAmit Nischal .flags = CLK_SET_RATE_PARENT,
101453361cdSAmit Nischal .ops = &clk_branch2_ops,
102453361cdSAmit Nischal },
103453361cdSAmit Nischal },
104453361cdSAmit Nischal };
105453361cdSAmit Nischal
106453361cdSAmit Nischal static struct clk_branch gpu_cc_cxo_clk = {
107453361cdSAmit Nischal .halt_reg = 0x109c,
108453361cdSAmit Nischal .halt_check = BRANCH_HALT,
109453361cdSAmit Nischal .clkr = {
110453361cdSAmit Nischal .enable_reg = 0x109c,
111453361cdSAmit Nischal .enable_mask = BIT(0),
112453361cdSAmit Nischal .hw.init = &(struct clk_init_data){
113453361cdSAmit Nischal .name = "gpu_cc_cxo_clk",
114453361cdSAmit Nischal .ops = &clk_branch2_ops,
115453361cdSAmit Nischal },
116453361cdSAmit Nischal },
117453361cdSAmit Nischal };
118453361cdSAmit Nischal
119453361cdSAmit Nischal static struct gdsc gpu_cx_gdsc = {
120453361cdSAmit Nischal .gdscr = 0x106c,
121453361cdSAmit Nischal .gds_hw_ctrl = 0x1540,
122cb81719eSDmitry Baryshkov .clk_dis_wait_val = 0x8,
123453361cdSAmit Nischal .pd = {
124453361cdSAmit Nischal .name = "gpu_cx_gdsc",
125453361cdSAmit Nischal },
126453361cdSAmit Nischal .pwrsts = PWRSTS_OFF_ON,
127453361cdSAmit Nischal .flags = VOTABLE,
128453361cdSAmit Nischal };
129453361cdSAmit Nischal
130453361cdSAmit Nischal static struct gdsc gpu_gx_gdsc = {
131453361cdSAmit Nischal .gdscr = 0x100c,
132453361cdSAmit Nischal .clamp_io_ctrl = 0x1508,
133453361cdSAmit Nischal .pd = {
134453361cdSAmit Nischal .name = "gpu_gx_gdsc",
1350638226dSJonathan Marek .power_on = gdsc_gx_do_nothing_enable,
136453361cdSAmit Nischal },
137453361cdSAmit Nischal .pwrsts = PWRSTS_OFF_ON,
138453361cdSAmit Nischal .flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR,
139453361cdSAmit Nischal };
140453361cdSAmit Nischal
141453361cdSAmit Nischal static struct clk_regmap *gpu_cc_sdm845_clocks[] = {
142453361cdSAmit Nischal [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
143453361cdSAmit Nischal [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
144453361cdSAmit Nischal [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
145453361cdSAmit Nischal [GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
146453361cdSAmit Nischal };
147453361cdSAmit Nischal
148453361cdSAmit Nischal static struct gdsc *gpu_cc_sdm845_gdscs[] = {
149453361cdSAmit Nischal [GPU_CX_GDSC] = &gpu_cx_gdsc,
150453361cdSAmit Nischal [GPU_GX_GDSC] = &gpu_gx_gdsc,
151453361cdSAmit Nischal };
152453361cdSAmit Nischal
153453361cdSAmit Nischal static const struct regmap_config gpu_cc_sdm845_regmap_config = {
154453361cdSAmit Nischal .reg_bits = 32,
155453361cdSAmit Nischal .reg_stride = 4,
156453361cdSAmit Nischal .val_bits = 32,
157453361cdSAmit Nischal .max_register = 0x8008,
158453361cdSAmit Nischal .fast_io = true,
159453361cdSAmit Nischal };
160453361cdSAmit Nischal
161453361cdSAmit Nischal static const struct qcom_cc_desc gpu_cc_sdm845_desc = {
162453361cdSAmit Nischal .config = &gpu_cc_sdm845_regmap_config,
163453361cdSAmit Nischal .clks = gpu_cc_sdm845_clocks,
164453361cdSAmit Nischal .num_clks = ARRAY_SIZE(gpu_cc_sdm845_clocks),
165453361cdSAmit Nischal .gdscs = gpu_cc_sdm845_gdscs,
166453361cdSAmit Nischal .num_gdscs = ARRAY_SIZE(gpu_cc_sdm845_gdscs),
167453361cdSAmit Nischal };
168453361cdSAmit Nischal
169453361cdSAmit Nischal static const struct of_device_id gpu_cc_sdm845_match_table[] = {
170453361cdSAmit Nischal { .compatible = "qcom,sdm845-gpucc" },
171453361cdSAmit Nischal { }
172453361cdSAmit Nischal };
173453361cdSAmit Nischal MODULE_DEVICE_TABLE(of, gpu_cc_sdm845_match_table);
174453361cdSAmit Nischal
gpu_cc_sdm845_probe(struct platform_device * pdev)175453361cdSAmit Nischal static int gpu_cc_sdm845_probe(struct platform_device *pdev)
176453361cdSAmit Nischal {
177453361cdSAmit Nischal struct regmap *regmap;
178453361cdSAmit Nischal unsigned int value, mask;
179453361cdSAmit Nischal
180453361cdSAmit Nischal regmap = qcom_cc_map(pdev, &gpu_cc_sdm845_desc);
181453361cdSAmit Nischal if (IS_ERR(regmap))
182453361cdSAmit Nischal return PTR_ERR(regmap);
183453361cdSAmit Nischal
184453361cdSAmit Nischal clk_fabia_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
185453361cdSAmit Nischal
186453361cdSAmit Nischal /*
187453361cdSAmit Nischal * Configure gpu_cc_cx_gmu_clk with recommended
188453361cdSAmit Nischal * wakeup/sleep settings
189453361cdSAmit Nischal */
190453361cdSAmit Nischal mask = CX_GMU_CBCR_WAKE_MASK << CX_GMU_CBCR_WAKE_SHIFT;
191453361cdSAmit Nischal mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT;
192453361cdSAmit Nischal value = 0xf << CX_GMU_CBCR_WAKE_SHIFT | 0xf << CX_GMU_CBCR_SLEEP_SHIFT;
193453361cdSAmit Nischal regmap_update_bits(regmap, 0x1098, mask, value);
194453361cdSAmit Nischal
195*9f93a0a4SLuo Jie return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sdm845_desc, regmap);
196453361cdSAmit Nischal }
197453361cdSAmit Nischal
198453361cdSAmit Nischal static struct platform_driver gpu_cc_sdm845_driver = {
199453361cdSAmit Nischal .probe = gpu_cc_sdm845_probe,
200453361cdSAmit Nischal .driver = {
201453361cdSAmit Nischal .name = "sdm845-gpucc",
202453361cdSAmit Nischal .of_match_table = gpu_cc_sdm845_match_table,
203453361cdSAmit Nischal },
204453361cdSAmit Nischal };
205453361cdSAmit Nischal
2060e3c498dSDmitry Baryshkov module_platform_driver(gpu_cc_sdm845_driver);
207453361cdSAmit Nischal
208453361cdSAmit Nischal MODULE_DESCRIPTION("QTI GPUCC SDM845 Driver");
209453361cdSAmit Nischal MODULE_LICENSE("GPL v2");
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