1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
4 */
5
6 #include <linux/clk-provider.h>
7 #include <linux/module.h>
8 #include <linux/platform_device.h>
9 #include <linux/regmap.h>
10
11 #include <dt-bindings/clock/qcom,nord-gpu2cc.h>
12
13 #include "clk-alpha-pll.h"
14 #include "clk-branch.h"
15 #include "clk-pll.h"
16 #include "clk-rcg.h"
17 #include "clk-regmap.h"
18 #include "clk-regmap-divider.h"
19 #include "clk-regmap-mux.h"
20 #include "common.h"
21 #include "gdsc.h"
22 #include "reset.h"
23
24 enum {
25 DT_BI_TCXO,
26 DT_GPLL0_OUT_MAIN,
27 DT_GPLL0_OUT_MAIN_DIV,
28 };
29
30 enum {
31 P_BI_TCXO,
32 P_GPLL0_OUT_MAIN,
33 P_GPLL0_OUT_MAIN_DIV,
34 P_GPU_2_CC_PLL0_OUT_MAIN,
35 P_GPU_2_CC_PLL1_OUT_MAIN,
36 };
37
38 static const struct pll_vco lucid_ole_vco[] = {
39 { 249600000, 2300000000, 0 },
40 };
41
42 /* 934.0 MHz Configuration */
43 static const struct alpha_pll_config gpu_2_cc_pll0_config = {
44 .l = 0x30,
45 .alpha = 0xa555,
46 .config_ctl_val = 0x20485699,
47 .config_ctl_hi_val = 0x00182261,
48 .config_ctl_hi1_val = 0x82aa299c,
49 .test_ctl_val = 0x00000000,
50 .test_ctl_hi_val = 0x00000003,
51 .test_ctl_hi1_val = 0x00009000,
52 .test_ctl_hi2_val = 0x00000034,
53 .user_ctl_val = 0x00000000,
54 .user_ctl_hi_val = 0x00400005,
55 };
56
57 static struct clk_alpha_pll gpu_2_cc_pll0 = {
58 .offset = 0x0,
59 .config = &gpu_2_cc_pll0_config,
60 .vco_table = lucid_ole_vco,
61 .num_vco = ARRAY_SIZE(lucid_ole_vco),
62 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
63 .clkr = {
64 .hw.init = &(const struct clk_init_data) {
65 .name = "gpu_2_cc_pll0",
66 .parent_data = &(const struct clk_parent_data) {
67 .index = DT_BI_TCXO,
68 },
69 .num_parents = 1,
70 .ops = &clk_alpha_pll_lucid_evo_ops,
71 },
72 },
73 };
74
75 /* 1100.0 MHz Configuration */
76 static const struct alpha_pll_config gpu_2_cc_pll1_config = {
77 .l = 0x39,
78 .alpha = 0x4aaa,
79 .config_ctl_val = 0x20485699,
80 .config_ctl_hi_val = 0x00182261,
81 .config_ctl_hi1_val = 0x82aa299c,
82 .test_ctl_val = 0x00000000,
83 .test_ctl_hi_val = 0x00000003,
84 .test_ctl_hi1_val = 0x00009000,
85 .test_ctl_hi2_val = 0x00000034,
86 .user_ctl_val = 0x00000000,
87 .user_ctl_hi_val = 0x00400005,
88 };
89
90 static struct clk_alpha_pll gpu_2_cc_pll1 = {
91 .offset = 0x1000,
92 .config = &gpu_2_cc_pll1_config,
93 .vco_table = lucid_ole_vco,
94 .num_vco = ARRAY_SIZE(lucid_ole_vco),
95 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
96 .clkr = {
97 .hw.init = &(const struct clk_init_data) {
98 .name = "gpu_2_cc_pll1",
99 .parent_data = &(const struct clk_parent_data) {
100 .index = DT_BI_TCXO,
101 },
102 .num_parents = 1,
103 .ops = &clk_alpha_pll_lucid_evo_ops,
104 },
105 },
106 };
107
108 static const struct parent_map gpu_2_cc_parent_map_0[] = {
109 { P_BI_TCXO, 0 },
110 { P_GPLL0_OUT_MAIN, 5 },
111 { P_GPLL0_OUT_MAIN_DIV, 6 },
112 };
113
114 static const struct clk_parent_data gpu_2_cc_parent_data_0[] = {
115 { .index = DT_BI_TCXO },
116 { .index = DT_GPLL0_OUT_MAIN },
117 { .index = DT_GPLL0_OUT_MAIN_DIV },
118 };
119
120 static const struct parent_map gpu_2_cc_parent_map_1[] = {
121 { P_BI_TCXO, 0 },
122 { P_GPU_2_CC_PLL0_OUT_MAIN, 1 },
123 { P_GPU_2_CC_PLL1_OUT_MAIN, 3 },
124 { P_GPLL0_OUT_MAIN, 5 },
125 { P_GPLL0_OUT_MAIN_DIV, 6 },
126 };
127
128 static const struct clk_parent_data gpu_2_cc_parent_data_1[] = {
129 { .index = DT_BI_TCXO },
130 { .hw = &gpu_2_cc_pll0.clkr.hw },
131 { .hw = &gpu_2_cc_pll1.clkr.hw },
132 { .index = DT_GPLL0_OUT_MAIN },
133 { .index = DT_GPLL0_OUT_MAIN_DIV },
134 };
135
136 static const struct parent_map gpu_2_cc_parent_map_2[] = {
137 { P_BI_TCXO, 0 },
138 { P_GPU_2_CC_PLL1_OUT_MAIN, 3 },
139 { P_GPLL0_OUT_MAIN, 5 },
140 { P_GPLL0_OUT_MAIN_DIV, 6 },
141 };
142
143 static const struct clk_parent_data gpu_2_cc_parent_data_2[] = {
144 { .index = DT_BI_TCXO },
145 { .hw = &gpu_2_cc_pll1.clkr.hw },
146 { .index = DT_GPLL0_OUT_MAIN },
147 { .index = DT_GPLL0_OUT_MAIN_DIV },
148 };
149
150 static const struct freq_tbl ftbl_gpu_2_cc_ff_clk_src[] = {
151 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
152 { }
153 };
154
155 static struct clk_rcg2 gpu_2_cc_ff_clk_src = {
156 .cmd_rcgr = 0x91c4,
157 .mnd_width = 0,
158 .hid_width = 5,
159 .parent_map = gpu_2_cc_parent_map_0,
160 .freq_tbl = ftbl_gpu_2_cc_ff_clk_src,
161 .hw_clk_ctrl = true,
162 .clkr.hw.init = &(const struct clk_init_data) {
163 .name = "gpu_2_cc_ff_clk_src",
164 .parent_data = gpu_2_cc_parent_data_0,
165 .num_parents = ARRAY_SIZE(gpu_2_cc_parent_data_0),
166 .flags = CLK_SET_RATE_PARENT,
167 .ops = &clk_rcg2_shared_ops,
168 },
169 };
170
171 static const struct freq_tbl ftbl_gpu_2_cc_gmu_clk_src[] = {
172 F(550000000, P_GPU_2_CC_PLL1_OUT_MAIN, 2, 0, 0),
173 { }
174 };
175
176 static struct clk_rcg2 gpu_2_cc_gmu_clk_src = {
177 .cmd_rcgr = 0x9174,
178 .mnd_width = 0,
179 .hid_width = 5,
180 .parent_map = gpu_2_cc_parent_map_1,
181 .freq_tbl = ftbl_gpu_2_cc_gmu_clk_src,
182 .hw_clk_ctrl = true,
183 .clkr.hw.init = &(const struct clk_init_data) {
184 .name = "gpu_2_cc_gmu_clk_src",
185 .parent_data = gpu_2_cc_parent_data_1,
186 .num_parents = ARRAY_SIZE(gpu_2_cc_parent_data_1),
187 .flags = CLK_SET_RATE_PARENT,
188 .ops = &clk_rcg2_shared_ops,
189 },
190 };
191
192 static struct clk_rcg2 gpu_2_cc_hub_clk_src = {
193 .cmd_rcgr = 0x91a8,
194 .mnd_width = 0,
195 .hid_width = 5,
196 .parent_map = gpu_2_cc_parent_map_2,
197 .freq_tbl = ftbl_gpu_2_cc_ff_clk_src,
198 .hw_clk_ctrl = true,
199 .clkr.hw.init = &(const struct clk_init_data) {
200 .name = "gpu_2_cc_hub_clk_src",
201 .parent_data = gpu_2_cc_parent_data_2,
202 .num_parents = ARRAY_SIZE(gpu_2_cc_parent_data_2),
203 .flags = CLK_SET_RATE_PARENT,
204 .ops = &clk_rcg2_shared_ops,
205 },
206 };
207
208 static struct clk_branch gpu_2_cc_ahb_clk = {
209 .halt_reg = 0x90cc,
210 .halt_check = BRANCH_HALT_VOTED,
211 .clkr = {
212 .enable_reg = 0x90cc,
213 .enable_mask = BIT(0),
214 .hw.init = &(const struct clk_init_data) {
215 .name = "gpu_2_cc_ahb_clk",
216 .parent_hws = (const struct clk_hw*[]) {
217 &gpu_2_cc_hub_clk_src.clkr.hw,
218 },
219 .num_parents = 1,
220 .flags = CLK_SET_RATE_PARENT,
221 .ops = &clk_branch2_ops,
222 },
223 },
224 };
225
226 static struct clk_branch gpu_2_cc_crc_ahb_clk = {
227 .halt_reg = 0x90d0,
228 .halt_check = BRANCH_HALT_VOTED,
229 .clkr = {
230 .enable_reg = 0x90d0,
231 .enable_mask = BIT(0),
232 .hw.init = &(const struct clk_init_data) {
233 .name = "gpu_2_cc_crc_ahb_clk",
234 .parent_hws = (const struct clk_hw*[]) {
235 &gpu_2_cc_hub_clk_src.clkr.hw,
236 },
237 .num_parents = 1,
238 .flags = CLK_SET_RATE_PARENT,
239 .ops = &clk_branch2_ops,
240 },
241 },
242 };
243
244 static struct clk_branch gpu_2_cc_cx_accu_shift_clk = {
245 .halt_reg = 0x9114,
246 .halt_check = BRANCH_HALT_VOTED,
247 .clkr = {
248 .enable_reg = 0x9114,
249 .enable_mask = BIT(0),
250 .hw.init = &(const struct clk_init_data) {
251 .name = "gpu_2_cc_cx_accu_shift_clk",
252 .ops = &clk_branch2_ops,
253 },
254 },
255 };
256
257 static struct clk_branch gpu_2_cc_cx_ff_clk = {
258 .halt_reg = 0x9100,
259 .halt_check = BRANCH_HALT,
260 .clkr = {
261 .enable_reg = 0x9100,
262 .enable_mask = BIT(0),
263 .hw.init = &(const struct clk_init_data) {
264 .name = "gpu_2_cc_cx_ff_clk",
265 .parent_hws = (const struct clk_hw*[]) {
266 &gpu_2_cc_ff_clk_src.clkr.hw,
267 },
268 .num_parents = 1,
269 .flags = CLK_SET_RATE_PARENT,
270 .ops = &clk_branch2_ops,
271 },
272 },
273 };
274
275 static struct clk_branch gpu_2_cc_cx_gmu_clk = {
276 .halt_reg = 0x90e8,
277 .halt_check = BRANCH_HALT_VOTED,
278 .clkr = {
279 .enable_reg = 0x90e8,
280 .enable_mask = BIT(0),
281 .hw.init = &(const struct clk_init_data) {
282 .name = "gpu_2_cc_cx_gmu_clk",
283 .parent_hws = (const struct clk_hw*[]) {
284 &gpu_2_cc_gmu_clk_src.clkr.hw,
285 },
286 .num_parents = 1,
287 .flags = CLK_SET_RATE_PARENT,
288 .ops = &clk_branch2_aon_ops,
289 },
290 },
291 };
292
293 static struct clk_branch gpu_2_cc_cxo_clk = {
294 .halt_reg = 0x90f8,
295 .halt_check = BRANCH_HALT,
296 .clkr = {
297 .enable_reg = 0x90f8,
298 .enable_mask = BIT(0),
299 .hw.init = &(const struct clk_init_data) {
300 .name = "gpu_2_cc_cxo_clk",
301 .ops = &clk_branch2_ops,
302 },
303 },
304 };
305
306 static struct clk_branch gpu_2_cc_freq_measure_clk = {
307 .halt_reg = 0x9008,
308 .halt_check = BRANCH_HALT,
309 .clkr = {
310 .enable_reg = 0x9008,
311 .enable_mask = BIT(0),
312 .hw.init = &(const struct clk_init_data) {
313 .name = "gpu_2_cc_freq_measure_clk",
314 .ops = &clk_branch2_ops,
315 },
316 },
317 };
318
319 static struct clk_branch gpu_2_cc_gpu_smmu_vote_clk = {
320 .halt_reg = 0x7000,
321 .halt_check = BRANCH_HALT_VOTED,
322 .clkr = {
323 .enable_reg = 0x7000,
324 .enable_mask = BIT(0),
325 .hw.init = &(const struct clk_init_data) {
326 .name = "gpu_2_cc_gpu_smmu_vote_clk",
327 .ops = &clk_branch2_ops,
328 },
329 },
330 };
331
332 static struct clk_branch gpu_2_cc_hub_aon_clk = {
333 .halt_reg = 0x91a4,
334 .halt_check = BRANCH_HALT,
335 .clkr = {
336 .enable_reg = 0x91a4,
337 .enable_mask = BIT(0),
338 .hw.init = &(const struct clk_init_data) {
339 .name = "gpu_2_cc_hub_aon_clk",
340 .parent_hws = (const struct clk_hw*[]) {
341 &gpu_2_cc_hub_clk_src.clkr.hw,
342 },
343 .num_parents = 1,
344 .flags = CLK_SET_RATE_PARENT,
345 .ops = &clk_branch2_aon_ops,
346 },
347 },
348 };
349
350 static struct clk_branch gpu_2_cc_hub_cx_int_clk = {
351 .halt_reg = 0x90fc,
352 .halt_check = BRANCH_HALT_VOTED,
353 .clkr = {
354 .enable_reg = 0x90fc,
355 .enable_mask = BIT(0),
356 .hw.init = &(const struct clk_init_data) {
357 .name = "gpu_2_cc_hub_cx_int_clk",
358 .parent_hws = (const struct clk_hw*[]) {
359 &gpu_2_cc_hub_clk_src.clkr.hw,
360 },
361 .num_parents = 1,
362 .flags = CLK_SET_RATE_PARENT,
363 .ops = &clk_branch2_aon_ops,
364 },
365 },
366 };
367
368 static struct clk_branch gpu_2_cc_memnoc_gfx_clk = {
369 .halt_reg = 0x9104,
370 .halt_check = BRANCH_HALT_VOTED,
371 .clkr = {
372 .enable_reg = 0x9104,
373 .enable_mask = BIT(0),
374 .hw.init = &(const struct clk_init_data) {
375 .name = "gpu_2_cc_memnoc_gfx_clk",
376 .ops = &clk_branch2_ops,
377 },
378 },
379 };
380
381 static struct clk_branch gpu_2_cc_mnd1x_0_gfx3d_clk = {
382 .halt_reg = 0x9164,
383 .halt_check = BRANCH_HALT,
384 .clkr = {
385 .enable_reg = 0x9164,
386 .enable_mask = BIT(0),
387 .hw.init = &(const struct clk_init_data) {
388 .name = "gpu_2_cc_mnd1x_0_gfx3d_clk",
389 .ops = &clk_branch2_ops,
390 },
391 },
392 };
393
394 static struct clk_branch gpu_2_cc_mnd1x_1_gfx3d_clk = {
395 .halt_reg = 0x9168,
396 .halt_check = BRANCH_HALT,
397 .clkr = {
398 .enable_reg = 0x9168,
399 .enable_mask = BIT(0),
400 .hw.init = &(const struct clk_init_data) {
401 .name = "gpu_2_cc_mnd1x_1_gfx3d_clk",
402 .ops = &clk_branch2_ops,
403 },
404 },
405 };
406
407 static struct clk_branch gpu_2_cc_sleep_clk = {
408 .halt_reg = 0x90e0,
409 .halt_check = BRANCH_HALT_SKIP,
410 .clkr = {
411 .enable_reg = 0x90e0,
412 .enable_mask = BIT(0),
413 .hw.init = &(const struct clk_init_data) {
414 .name = "gpu_2_cc_sleep_clk",
415 .ops = &clk_branch2_ops,
416 },
417 },
418 };
419
420 static struct gdsc gpu_2_cc_cx_gdsc = {
421 .gdscr = 0x9090,
422 .gds_hw_ctrl = 0x90a4,
423 .en_rest_wait_val = 0x2,
424 .en_few_wait_val = 0x2,
425 .clk_dis_wait_val = 0xf,
426 .pd = {
427 .name = "gpu_2_cc_cx_gdsc",
428 },
429 .pwrsts = PWRSTS_OFF_ON,
430 .flags = VOTABLE | RETAIN_FF_ENABLE,
431 };
432
433 static struct gdsc gpu_2_cc_gx_gdsc = {
434 .gdscr = 0x9034,
435 .clamp_io_ctrl = 0x9504,
436 .en_rest_wait_val = 0x2,
437 .en_few_wait_val = 0x2,
438 .clk_dis_wait_val = 0xf,
439 .pd = {
440 .name = "gpu_2_cc_gx_gdsc",
441 .power_on = gdsc_gx_do_nothing_enable,
442 },
443 .pwrsts = PWRSTS_OFF_ON,
444 .flags = CLAMP_IO | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
445 };
446
447 static struct clk_regmap *gpu_2_cc_nord_clocks[] = {
448 [GPU_2_CC_AHB_CLK] = &gpu_2_cc_ahb_clk.clkr,
449 [GPU_2_CC_CRC_AHB_CLK] = &gpu_2_cc_crc_ahb_clk.clkr,
450 [GPU_2_CC_CX_ACCU_SHIFT_CLK] = &gpu_2_cc_cx_accu_shift_clk.clkr,
451 [GPU_2_CC_CX_FF_CLK] = &gpu_2_cc_cx_ff_clk.clkr,
452 [GPU_2_CC_CX_GMU_CLK] = &gpu_2_cc_cx_gmu_clk.clkr,
453 [GPU_2_CC_CXO_CLK] = &gpu_2_cc_cxo_clk.clkr,
454 [GPU_2_CC_FF_CLK_SRC] = &gpu_2_cc_ff_clk_src.clkr,
455 [GPU_2_CC_FREQ_MEASURE_CLK] = &gpu_2_cc_freq_measure_clk.clkr,
456 [GPU_2_CC_GMU_CLK_SRC] = &gpu_2_cc_gmu_clk_src.clkr,
457 [GPU_2_CC_GPU_SMMU_VOTE_CLK] = &gpu_2_cc_gpu_smmu_vote_clk.clkr,
458 [GPU_2_CC_HUB_AON_CLK] = &gpu_2_cc_hub_aon_clk.clkr,
459 [GPU_2_CC_HUB_CLK_SRC] = &gpu_2_cc_hub_clk_src.clkr,
460 [GPU_2_CC_HUB_CX_INT_CLK] = &gpu_2_cc_hub_cx_int_clk.clkr,
461 [GPU_2_CC_MEMNOC_GFX_CLK] = &gpu_2_cc_memnoc_gfx_clk.clkr,
462 [GPU_2_CC_MND1X_0_GFX3D_CLK] = &gpu_2_cc_mnd1x_0_gfx3d_clk.clkr,
463 [GPU_2_CC_MND1X_1_GFX3D_CLK] = &gpu_2_cc_mnd1x_1_gfx3d_clk.clkr,
464 [GPU_2_CC_PLL0] = &gpu_2_cc_pll0.clkr,
465 [GPU_2_CC_PLL1] = &gpu_2_cc_pll1.clkr,
466 [GPU_2_CC_SLEEP_CLK] = &gpu_2_cc_sleep_clk.clkr,
467 };
468
469 static struct gdsc *gpu_2_cc_nord_gdscs[] = {
470 [GPU_2_CC_CX_GDSC] = &gpu_2_cc_cx_gdsc,
471 [GPU_2_CC_GX_GDSC] = &gpu_2_cc_gx_gdsc,
472 };
473
474 static const struct qcom_reset_map gpu_2_cc_nord_resets[] = {
475 [GPU_2_CC_ACD_BCR] = { 0x918c },
476 [GPU_2_CC_CB_BCR] = { 0x9198 },
477 [GPU_2_CC_CX_BCR] = { 0x908c },
478 [GPU_2_CC_FAST_HUB_BCR] = { 0x91a0 },
479 [GPU_2_CC_FF_BCR] = { 0x91c0 },
480 [GPU_2_CC_GFX3D_AON_BCR] = { 0x9118 },
481 [GPU_2_CC_GMU_BCR] = { 0x9170 },
482 [GPU_2_CC_GX_BCR] = { 0x9030 },
483 [GPU_2_CC_XO_BCR] = { 0x9000 },
484 };
485
486 static struct clk_alpha_pll *gpu_2_cc_nord_plls[] = {
487 &gpu_2_cc_pll0,
488 &gpu_2_cc_pll1,
489 };
490
491 static const u32 gpu_2_cc_nord_critical_cbcrs[] = {
492 0x9004, /* GPU_2_CC_CXO_AON_CLK */
493 0x900c, /* GPU_2_CC_DEMET_CLK */
494 };
495
496 static const struct regmap_config gpu_2_cc_nord_regmap_config = {
497 .reg_bits = 32,
498 .reg_stride = 4,
499 .val_bits = 32,
500 .max_register = 0x9ff0,
501 .fast_io = true,
502 };
503
504 static const struct qcom_cc_driver_data gpu_2_cc_nord_driver_data = {
505 .alpha_plls = gpu_2_cc_nord_plls,
506 .num_alpha_plls = ARRAY_SIZE(gpu_2_cc_nord_plls),
507 .clk_cbcrs = gpu_2_cc_nord_critical_cbcrs,
508 .num_clk_cbcrs = ARRAY_SIZE(gpu_2_cc_nord_critical_cbcrs),
509 };
510
511 static const struct qcom_cc_desc gpu_2_cc_nord_desc = {
512 .config = &gpu_2_cc_nord_regmap_config,
513 .clks = gpu_2_cc_nord_clocks,
514 .num_clks = ARRAY_SIZE(gpu_2_cc_nord_clocks),
515 .resets = gpu_2_cc_nord_resets,
516 .num_resets = ARRAY_SIZE(gpu_2_cc_nord_resets),
517 .gdscs = gpu_2_cc_nord_gdscs,
518 .num_gdscs = ARRAY_SIZE(gpu_2_cc_nord_gdscs),
519 .use_rpm = true,
520 .driver_data = &gpu_2_cc_nord_driver_data,
521 };
522
523 static const struct of_device_id gpu_2_cc_nord_match_table[] = {
524 { .compatible = "qcom,nord-gpu2cc" },
525 { }
526 };
527 MODULE_DEVICE_TABLE(of, gpu_2_cc_nord_match_table);
528
gpu_2_cc_nord_probe(struct platform_device * pdev)529 static int gpu_2_cc_nord_probe(struct platform_device *pdev)
530 {
531 return qcom_cc_probe(pdev, &gpu_2_cc_nord_desc);
532 }
533
534 static struct platform_driver gpu_2_cc_nord_driver = {
535 .probe = gpu_2_cc_nord_probe,
536 .driver = {
537 .name = "gpu2cc-nord",
538 .of_match_table = gpu_2_cc_nord_match_table,
539 },
540 };
541
542 module_platform_driver(gpu_2_cc_nord_driver);
543
544 MODULE_DESCRIPTION("QTI GPU2CC Nord Driver");
545 MODULE_LICENSE("GPL");
546