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Searched refs:BCS0 (Results 1 – 16 of 16) sorted by relevance

/linux/drivers/gpu/drm/i915/
H A Di915_pci.c265 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
313 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
380 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
388 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
447 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
453 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
498 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
513 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
560 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
581 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
[all …]
H A Di915_drv.h614 ENGINE_INSTANCES_MASK(gt, BCS0, I915_MAX_BCS)
H A Di915_gpu_error.c1305 case BCS0: in engine_record_registers()
/linux/drivers/gpu/drm/i915/gvt/
H A Dmmio_context.c81 {BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
82 {BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
83 {BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
84 {BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
85 {BCS0, RING_EXCC(BLT_RING_BASE), 0xffff, false}, /* 0x22028 */
135 {BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
136 {BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
137 {BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
138 {BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
139 {BCS0, RING_EXCC(BLT_RING_BASE), 0xffff, false}, /* 0x22028 */
[all …]
H A Dexeclist.c50 [BCS0] = BCS_AS_CONTEXT_SWITCH,
H A Dcmd_parser.c430 #define R_BCS BIT(BCS0)
620 [BCS0] = {
1053 if (s->engine->id == BCS0 && in cmd_handler_lri()
1158 [BCS0] = {
H A Dhandlers.c343 engine_mask |= BIT(BCS0); in gdrst_mmio_write()
2107 id = BCS0; in gvt_reg_tlb_control_handler()
/linux/drivers/gpu/drm/i915/gt/
H A Dintel_engine_types.h113 BCS0, enumerator
122 #define _BCS(n) (BCS0 + (n))
H A Dintel_engine_cs.c71 [BCS0] = {
403 [BCS0] = GEN11_GRDOM_BLT, in get_reset_domain()
436 [BCS0] = GEN6_GRDOM_BLT, in get_reset_domain()
1466 if (i915_ggtt_require_binder(engine->i915) && engine->id == BCS0) { in engine_init_common()
1705 [BCS0] = MSG_IDLE_BCS, in __cs_pending_mi_force_wakes()
H A Dintel_engine_user.c166 [COPY_ENGINE_CLASS] = { BCS0, 1 }, in legacy_ring_idx()
H A Dintel_mocs.c574 [BCS0] = __GEN9_BCS0_MOCS0, in mocs_offset()
H A Dgen8_engine_cs.c173 case BCS0: in gen12_get_aux_inv_reg()
H A Dintel_ring_submission.c97 case BCS0: in set_hwsp()
H A Dintel_ggtt.c307 ce = gt->engine[BCS0]->bind_context; in gen8_ggtt_bind_get_ce()
H A Dintel_execlists_submission.c3494 [BCS0] = GEN8_BCS_IRQ_SHIFT, in logical_ring_default_irqs()
/linux/drivers/gpu/drm/i915/gem/
H A Di915_gem_execbuffer.c2474 [I915_EXEC_BLT] = BCS0,