| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| H A D | dcn314_smu.c | 45 #ifdef BASE_INNER
46 #undef BASE_INNER
49 #define BASE_INNER(seg) MP1_BASE__INST0_SEG ## seg macro
51 #define BASE(seg) BASE_INNER(seg)
|
| /linux/drivers/gpu/drm/amd/display/dc/gpio/dcn21/ |
| H A D | hw_factory_dcn21.c | 50 #undef BASE_INNER
51 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg macro
53 #define BASE(seg) BASE_INNER(seg)
|
| H A D | hw_translate_dcn21.c | 49 #undef BASE_INNER
50 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg macro
52 #define BASE(seg) BASE_INNER(seg)
|
| /linux/drivers/gpu/drm/amd/display/dc/gpio/dcn32/ |
| H A D | hw_factory_dcn32.c | 52 #undef BASE_INNER
53 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg macro
55 #define BASE(seg) BASE_INNER(seg)
|
| H A D | hw_translate_dcn32.c | 47 #undef BASE_INNER
48 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg macro
50 #define BASE(seg) BASE_INNER(seg)
|
| /linux/drivers/gpu/drm/amd/display/dc/gpio/dcn30/ |
| H A D | hw_factory_dcn30.c | 59 #undef BASE_INNER
60 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg macro
62 #define BASE(seg) BASE_INNER(seg)
|
| H A D | hw_translate_dcn30.c | 54 #undef BASE_INNER
55 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg macro
57 #define BASE(seg) BASE_INNER(seg)
|
| /linux/drivers/gpu/drm/amd/display/dc/gpio/dcn315/ |
| H A D | hw_factory_dcn315.c | 56 #undef BASE_INNER
57 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg macro
59 #define BASE(seg) BASE_INNER(seg)
|
| H A D | hw_translate_dcn315.c | 49 #undef BASE_INNER
50 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg macro
52 #define BASE(seg) BASE_INNER(seg)
|
| /linux/drivers/gpu/drm/amd/display/dc/gpio/dcn401/ |
| H A D | hw_translate_dcn401.c | 22 #undef BASE_INNER
23 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg macro
25 #define BASE(seg) BASE_INNER(seg)
|
| H A D | hw_factory_dcn401.c | 32 #undef BASE_INNER
33 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg macro
35 #define BASE(seg) BASE_INNER(seg)
|
| /linux/drivers/gpu/drm/amd/display/dc/gpio/dcn20/ |
| H A D | hw_factory_dcn20.c | 52 #undef BASE_INNER
53 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg macro
55 #define BASE(seg) BASE_INNER(seg)
|
| H A D | hw_translate_dcn20.c | 49 #undef BASE_INNER
50 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg macro
52 #define BASE(seg) BASE_INNER(seg)
|
| /linux/drivers/gpu/drm/amd/display/dc/gpio/dce120/ |
| H A D | hw_factory_dce120.c | 53 #define BASE_INNER(seg) \ macro
58 BASE_INNER(seg)
|
| /linux/drivers/gpu/drm/amd/display/dc/gpio/dcn10/ |
| H A D | hw_factory_dcn10.c | 50 #define BASE_INNER(seg) \ macro
55 BASE_INNER(seg)
|
| H A D | hw_translate_dcn10.c | 44 #define BASE_INNER(seg) \ macro
49 BASE_INNER(seg)
|
| /linux/drivers/gpu/drm/amd/display/dmub/src/ |
| H A D | dmub_dcn301.c | 34 #define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg macro
|
| H A D | dmub_dcn303.c | 35 #define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg macro
|
| H A D | dmub_dcn21.c | 34 #define BASE_INNER(seg) DMU_BASE__INST0_SEG##seg macro
|
| H A D | dmub_dcn302.c | 34 #define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg macro
|
| H A D | dmub_dcn316.c | 40 #define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg macro
|
| H A D | dmub_dcn315.c | 40 #define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg macro
|
| H A D | dmub_dcn314.c | 40 #define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg macro
|
| H A D | dmub_dcn351.c | 11 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg] macro
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/ |
| H A D | dcn201_clk_mgr.c | 45 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg macro
47 #define BASE(seg) BASE_INNER(seg)
|