1*ebb20fc1SHamza Mahfooz /* SPDX-License-Identifier: MIT */ 2*ebb20fc1SHamza Mahfooz /* Copyright 2024 Advanced Micro Devices, Inc. */ 3*ebb20fc1SHamza Mahfooz 4*ebb20fc1SHamza Mahfooz #include "../dmub_srv.h" 5*ebb20fc1SHamza Mahfooz #include "dmub_reg.h" 6*ebb20fc1SHamza Mahfooz #include "dmub_dcn351.h" 7*ebb20fc1SHamza Mahfooz 8*ebb20fc1SHamza Mahfooz #include "dcn/dcn_3_5_1_offset.h" 9*ebb20fc1SHamza Mahfooz #include "dcn/dcn_3_5_1_sh_mask.h" 10*ebb20fc1SHamza Mahfooz 11*ebb20fc1SHamza Mahfooz #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg] 12*ebb20fc1SHamza Mahfooz #define CTX dmub 13*ebb20fc1SHamza Mahfooz #define REGS dmub->regs_dcn35 14*ebb20fc1SHamza Mahfooz #define REG_OFFSET_EXP(reg_name) BASE(reg##reg_name##_BASE_IDX) + reg##reg_name 15*ebb20fc1SHamza Mahfooz dmub_srv_dcn351_regs_init(struct dmub_srv * dmub,struct dc_context * ctx)16*ebb20fc1SHamza Mahfoozvoid dmub_srv_dcn351_regs_init(struct dmub_srv *dmub, struct dc_context *ctx) 17*ebb20fc1SHamza Mahfooz { 18*ebb20fc1SHamza Mahfooz struct dmub_srv_dcn35_regs *regs = dmub->regs_dcn35; 19*ebb20fc1SHamza Mahfooz #define REG_STRUCT regs 20*ebb20fc1SHamza Mahfooz 21*ebb20fc1SHamza Mahfooz #define DMUB_SR(reg) REG_STRUCT->offset.reg = REG_OFFSET_EXP(reg); 22*ebb20fc1SHamza Mahfooz DMUB_DCN35_REGS() 23*ebb20fc1SHamza Mahfooz DMCUB_INTERNAL_REGS() 24*ebb20fc1SHamza Mahfooz #undef DMUB_SR 25*ebb20fc1SHamza Mahfooz 26*ebb20fc1SHamza Mahfooz #define DMUB_SF(reg, field) REG_STRUCT->mask.reg##__##field = FD_MASK(reg, field); 27*ebb20fc1SHamza Mahfooz DMUB_DCN35_FIELDS() 28*ebb20fc1SHamza Mahfooz #undef DMUB_SF 29*ebb20fc1SHamza Mahfooz 30*ebb20fc1SHamza Mahfooz #define DMUB_SF(reg, field) REG_STRUCT->shift.reg##__##field = FD_SHIFT(reg, field); 31*ebb20fc1SHamza Mahfooz DMUB_DCN35_FIELDS() 32*ebb20fc1SHamza Mahfooz #undef DMUB_SF 33*ebb20fc1SHamza Mahfooz #undef REG_STRUCT 34*ebb20fc1SHamza Mahfooz } 35