1 /*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 /*
27 * Pre-requisites: headers required by header of this unit
28 */
29 #include "hw_translate_dcn21.h"
30
31 #include "dm_services.h"
32 #include "include/gpio_types.h"
33 #include "../hw_translate.h"
34
35 #include "dcn/dcn_2_1_0_offset.h"
36 #include "dcn/dcn_2_1_0_sh_mask.h"
37 #include "renoir_ip_offset.h"
38
39
40
41
42 /* begin *********************
43 * macros to expend register list macro defined in HW object header file */
44
45 /* DCN */
46 #define block HPD
47 #define reg_num 0
48
49 #undef BASE_INNER
50 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
51
52 #define BASE(seg) BASE_INNER(seg)
53
54 #undef REG
55 #define REG(reg_name)\
56 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
57 #define SF_HPD(reg_name, field_name, post_fix)\
58 .field_name = reg_name ## __ ## field_name ## post_fix
59
60 /* macros to expend register list macro defined in HW object header file
61 * end *********************/
62
63
offset_to_id(uint32_t offset,uint32_t mask,enum gpio_id * id,uint32_t * en)64 static bool offset_to_id(
65 uint32_t offset,
66 uint32_t mask,
67 enum gpio_id *id,
68 uint32_t *en)
69 {
70 switch (offset) {
71 /* GENERIC */
72 case REG(DC_GPIO_GENERIC_A):
73 *id = GPIO_ID_GENERIC;
74 switch (mask) {
75 case DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK:
76 *en = GPIO_GENERIC_A;
77 return true;
78 case DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK:
79 *en = GPIO_GENERIC_B;
80 return true;
81 case DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK:
82 *en = GPIO_GENERIC_C;
83 return true;
84 case DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK:
85 *en = GPIO_GENERIC_D;
86 return true;
87 case DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK:
88 *en = GPIO_GENERIC_E;
89 return true;
90 case DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK:
91 *en = GPIO_GENERIC_F;
92 return true;
93 case DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK:
94 *en = GPIO_GENERIC_G;
95 return true;
96 default:
97 ASSERT_CRITICAL(false);
98 return false;
99 }
100 break;
101 /* HPD */
102 case REG(DC_GPIO_HPD_A):
103 *id = GPIO_ID_HPD;
104 switch (mask) {
105 case DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK:
106 *en = GPIO_HPD_1;
107 return true;
108 case DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK:
109 *en = GPIO_HPD_2;
110 return true;
111 case DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK:
112 *en = GPIO_HPD_3;
113 return true;
114 case DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK:
115 *en = GPIO_HPD_4;
116 return true;
117 case DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK:
118 *en = GPIO_HPD_5;
119 return true;
120 case DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK:
121 *en = GPIO_HPD_6;
122 return true;
123 default:
124 ASSERT_CRITICAL(false);
125 return false;
126 }
127 break;
128 /* REG(DC_GPIO_GENLK_MASK */
129 case REG(DC_GPIO_GENLK_A):
130 *id = GPIO_ID_GSL;
131 switch (mask) {
132 case DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK:
133 *en = GPIO_GSL_GENLOCK_CLOCK;
134 return true;
135 case DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK:
136 *en = GPIO_GSL_GENLOCK_VSYNC;
137 return true;
138 case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK:
139 *en = GPIO_GSL_SWAPLOCK_A;
140 return true;
141 case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK:
142 *en = GPIO_GSL_SWAPLOCK_B;
143 return true;
144 default:
145 ASSERT_CRITICAL(false);
146 return false;
147 }
148 break;
149 /* DDC */
150 /* we don't care about the GPIO_ID for DDC
151 * in DdcHandle it will use GPIO_ID_DDC_DATA/GPIO_ID_DDC_CLOCK
152 * directly in the create method
153 */
154 case REG(DC_GPIO_DDC1_A):
155 *en = GPIO_DDC_LINE_DDC1;
156 return true;
157 case REG(DC_GPIO_DDC2_A):
158 *en = GPIO_DDC_LINE_DDC2;
159 return true;
160 case REG(DC_GPIO_DDC3_A):
161 *en = GPIO_DDC_LINE_DDC3;
162 return true;
163 case REG(DC_GPIO_DDC4_A):
164 *en = GPIO_DDC_LINE_DDC4;
165 return true;
166 case REG(DC_GPIO_DDC5_A):
167 *en = GPIO_DDC_LINE_DDC5;
168 return true;
169 case REG(DC_GPIO_DDCVGA_A):
170 *en = GPIO_DDC_LINE_DDC_VGA;
171 return true;
172
173 /*
174 * case REG(DC_GPIO_I2CPAD_A): not exit
175 * case REG(DC_GPIO_PWRSEQ_A):
176 * case REG(DC_GPIO_PAD_STRENGTH_1):
177 * case REG(DC_GPIO_PAD_STRENGTH_2):
178 * case REG(DC_GPIO_DEBUG):
179 */
180 /* UNEXPECTED */
181 default:
182 /* case REG(DC_GPIO_SYNCA_A): not exist */
183 ASSERT_CRITICAL(false);
184 return false;
185 }
186 }
187
id_to_offset(enum gpio_id id,uint32_t en,struct gpio_pin_info * info)188 static bool id_to_offset(
189 enum gpio_id id,
190 uint32_t en,
191 struct gpio_pin_info *info)
192 {
193 bool result = true;
194
195 switch (id) {
196 case GPIO_ID_DDC_DATA:
197 info->mask = DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK;
198 switch (en) {
199 case GPIO_DDC_LINE_DDC1:
200 info->offset = REG(DC_GPIO_DDC1_A);
201 break;
202 case GPIO_DDC_LINE_DDC2:
203 info->offset = REG(DC_GPIO_DDC2_A);
204 break;
205 case GPIO_DDC_LINE_DDC3:
206 info->offset = REG(DC_GPIO_DDC3_A);
207 break;
208 case GPIO_DDC_LINE_DDC4:
209 info->offset = REG(DC_GPIO_DDC4_A);
210 break;
211 case GPIO_DDC_LINE_DDC5:
212 info->offset = REG(DC_GPIO_DDC5_A);
213 break;
214 case GPIO_DDC_LINE_DDC_VGA:
215 info->offset = REG(DC_GPIO_DDCVGA_A);
216 break;
217 case GPIO_DDC_LINE_I2C_PAD:
218 default:
219 ASSERT_CRITICAL(false);
220 result = false;
221 }
222 break;
223 case GPIO_ID_DDC_CLOCK:
224 info->mask = DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK;
225 switch (en) {
226 case GPIO_DDC_LINE_DDC1:
227 info->offset = REG(DC_GPIO_DDC1_A);
228 break;
229 case GPIO_DDC_LINE_DDC2:
230 info->offset = REG(DC_GPIO_DDC2_A);
231 break;
232 case GPIO_DDC_LINE_DDC3:
233 info->offset = REG(DC_GPIO_DDC3_A);
234 break;
235 case GPIO_DDC_LINE_DDC4:
236 info->offset = REG(DC_GPIO_DDC4_A);
237 break;
238 case GPIO_DDC_LINE_DDC5:
239 info->offset = REG(DC_GPIO_DDC5_A);
240 break;
241 case GPIO_DDC_LINE_DDC_VGA:
242 info->offset = REG(DC_GPIO_DDCVGA_A);
243 break;
244 case GPIO_DDC_LINE_I2C_PAD:
245 default:
246 ASSERT_CRITICAL(false);
247 result = false;
248 }
249 break;
250 case GPIO_ID_GENERIC:
251 info->offset = REG(DC_GPIO_GENERIC_A);
252 switch (en) {
253 case GPIO_GENERIC_A:
254 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK;
255 break;
256 case GPIO_GENERIC_B:
257 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK;
258 break;
259 case GPIO_GENERIC_C:
260 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK;
261 break;
262 case GPIO_GENERIC_D:
263 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK;
264 break;
265 case GPIO_GENERIC_E:
266 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK;
267 break;
268 case GPIO_GENERIC_F:
269 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK;
270 break;
271 case GPIO_GENERIC_G:
272 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK;
273 break;
274 default:
275 ASSERT_CRITICAL(false);
276 result = false;
277 }
278 break;
279 case GPIO_ID_HPD:
280 info->offset = REG(DC_GPIO_HPD_A);
281 switch (en) {
282 case GPIO_HPD_1:
283 info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK;
284 break;
285 case GPIO_HPD_2:
286 info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK;
287 break;
288 case GPIO_HPD_3:
289 info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK;
290 break;
291 case GPIO_HPD_4:
292 info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK;
293 break;
294 case GPIO_HPD_5:
295 info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK;
296 break;
297 case GPIO_HPD_6:
298 info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK;
299 break;
300 default:
301 ASSERT_CRITICAL(false);
302 result = false;
303 }
304 break;
305 case GPIO_ID_GSL:
306 switch (en) {
307 case GPIO_GSL_GENLOCK_CLOCK:
308 /*not implmented*/
309 ASSERT_CRITICAL(false);
310 result = false;
311 break;
312 case GPIO_GSL_GENLOCK_VSYNC:
313 /*not implmented*/
314 ASSERT_CRITICAL(false);
315 result = false;
316 break;
317 case GPIO_GSL_SWAPLOCK_A:
318 /*not implmented*/
319 ASSERT_CRITICAL(false);
320 result = false;
321 break;
322 case GPIO_GSL_SWAPLOCK_B:
323 /*not implmented*/
324 ASSERT_CRITICAL(false);
325 result = false;
326
327 break;
328 default:
329 ASSERT_CRITICAL(false);
330 result = false;
331 }
332 break;
333 case GPIO_ID_SYNC:
334 case GPIO_ID_VIP_PAD:
335 default:
336 ASSERT_CRITICAL(false);
337 result = false;
338 }
339
340 if (result) {
341 info->offset_y = info->offset + 2;
342 info->offset_en = info->offset + 1;
343 info->offset_mask = info->offset - 1;
344
345 info->mask_y = info->mask;
346 info->mask_en = info->mask;
347 info->mask_mask = info->mask;
348 }
349
350 return result;
351 }
352
353 /* function table */
354 static const struct hw_translate_funcs funcs = {
355 .offset_to_id = offset_to_id,
356 .id_to_offset = id_to_offset,
357 };
358
359 /*
360 * dal_hw_translate_dcn10_init
361 *
362 * @brief
363 * Initialize Hw translate function pointers.
364 *
365 * @param
366 * struct hw_translate *tr - [out] struct of function pointers
367 *
368 */
dal_hw_translate_dcn21_init(struct hw_translate * tr)369 void dal_hw_translate_dcn21_init(struct hw_translate *tr)
370 {
371 tr->funcs = &funcs;
372 }
373
374