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Searched refs:v4i32 (Results 1 – 25 of 117) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrAltivec.td408 [(int_ppc_altivec_mtvscr v4i32:$VB)]>;
420 [(set v4i32:$RST, (int_ppc_altivec_lvewx ForceXForm:$addr))]>;
423 [(set v4i32:$RST, (int_ppc_altivec_lvx ForceXForm:$addr))]>;
426 [(set v4i32:$RST, (int_ppc_altivec_lvxl ForceXForm:$addr))]>;
447 [(int_ppc_altivec_stvewx v4i32:$RST, ForceXForm:$addr)]>;
450 [(int_ppc_altivec_stvx v4i32:$RST, ForceXForm:$addr)]>;
453 [(int_ppc_altivec_stvxl v4i32:$RST, ForceXForm:$addr)]>;
478 v4i32, v4i32, v16i8>;
479 def VSEL : VA1a_Int_Ty<42, "vsel", int_ppc_altivec_vsel, v4i32>;
501 [(set v4i32:$VD, (add v4i32:$VA, v4i32:$VB))]>;
[all …]
H A DPPCInstrP10.td66 SDTCisVT<0, v512i1>, SDTCisVT<1, v4i32>, SDTCisVT<2, v4i32>,
67 SDTCisVT<3, v4i32>, SDTCisVT<4, v4i32>
70 SDTCisVT<0, v256i1>, SDTCisVT<1, v4i32>, SDTCisVT<2, v4i32>
73 SDTCisVT<0, v4i32>, SDTCisVT<1, v512i1>, SDTCisPtrTy<2>
76 SDTCisVT<0, v4i32>, SDTCisVT<1, v256i1>, SDTCisPtrTy<2>
1150 def : Pat<(v256i1 (PPCPairBuild v4i32:$vs1, v4i32:$vs0)),
1154 def : Pat<(v4i32 (PPCPairExtractVsx vsrpevenrc:$v, 0)),
1155 (v4i32 (EXTRACT_SUBREG $v, sub_vsx0))>;
1156 def : Pat<(v4i32 (PPCPairExtractVsx vsrpevenrc:$v, 1)),
1157 (v4i32 (EXTRACT_SUBREG $v, sub_vsx1))>;
[all …]
H A DPPCInstrVSX.td88 SDTCisVT<2, v2f64>, SDTCisVT<3, v4i32>]>;
684 int_ppc_vsx_xvcmpeqsp, v4i32, v4f32>;
690 int_ppc_vsx_xvcmpgesp, v4i32, v4f32>;
696 int_ppc_vsx_xvcmpgtsp, v4i32, v4f32>;
823 [(set v4i32:$XT, (int_ppc_vsx_xvcvdpsxws v2f64:$XB))]>;
831 [(set v4i32:$XT, (int_ppc_vsx_xvcvdpuxws v2f64:$XB))]>;
844 [(set v4i32:$XT, (any_fp_to_sint v4f32:$XB))]>;
852 [(set v4i32:$XT, (any_fp_to_uint v4f32:$XB))]>;
864 [(set v4f32:$XT, (any_sint_to_fp v4i32:$XB))]>;
876 [(set v4f32:$XT, (any_uint_to_fp v4i32:$XB))]>;
[all …]
H A DREADME_P9.txt16 (set v2i64:$vD, (int_ppc_altivec_vextractuw v4i32:$vA, imm:$UIMM))
25 (set i64:$rD, (int_ppc_altivec_vextuwlx i64:$rA, v4i32:$vB))
30 (set i64:$rD, (int_ppc_altivec_vextuwrx i64:$rA, v4i32:$vB))
35 (set v4i32:$vD, (int_ppc_altivec_vinserth v4i32:$vA, imm:$UIMM))
48 (set v4i32:$vD, (cttz v4i32:$vB)) // vctzw
53 (set v4i32:$vD, (sext v4i8:$vB))
61 (set v4i32:$vD, (sext v4i16:$vB))
94 (set v4i32:$rT, (ineg v4i32:$rA)) // vnegw
99 (set v4i32:$rD, (int_ppc_altivec_vprtybw v4i32:$vB))
112 VX1_Int_Ty<389, "vrlwnm", int_ppc_altivec_vrlwnm, v4i32>;
[all …]
/freebsd/contrib/llvm-project/clang/lib/Headers/
H A Dlsxintrin.h22 typedef int v4i32 __attribute__((vector_size(16), aligned(16))); typedef
54 return (__m128i)__builtin_lsx_vsll_w((v4i32)_1, (v4i32)_2); in __lsx_vsll_w()
70 ((__m128i)__builtin_lsx_vslli_w((v4i32)(_1), (_2)))
90 return (__m128i)__builtin_lsx_vsra_w((v4i32)_1, (v4i32)_2); in __lsx_vsra_w()
106 ((__m128i)__builtin_lsx_vsrai_w((v4i32)(_1), (_2)))
126 return (__m128i)__builtin_lsx_vsrar_w((v4i32)_1, (v4i32)_2); in __lsx_vsrar_w()
142 ((__m128i)__builtin_lsx_vsrari_w((v4i32)(_1), (_2)))
162 return (__m128i)__builtin_lsx_vsrl_w((v4i32)_1, (v4i32)_2); in __lsx_vsrl_w()
178 ((__m128i)__builtin_lsx_vsrli_w((v4i32)(_1), (_2)))
198 return (__m128i)__builtin_lsx_vsrlr_w((v4i32)_1, (v4i32)_2); in __lsx_vsrlr_w()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchLSXInstrInfo.td152 : PatFrags<(ops), [(bitconvert (v4i32 (build_vector))),
218 (v4i32 (build_vector node:$e0, node:$e0,
1261 def PseudoVBNZ_W : VecCond<loongarch_vall_nonzero, v4i32>;
1267 def PseudoVBZ_W : VecCond<loongarch_vall_zero, v4i32>;
1292 def : Pat<(v4i32 (OpNode (v4i32 LSX128:$vj))),
1310 def : Pat<(OpNode (v4i32 LSX128:$vj), (v4i32 LSX128:$vk)),
1328 def : Pat<(OpNode (v4i32 LSX128:$vj), (v4i32 LSX128:$vk)),
1339 def : Pat<(OpNode (v4i32 LSX128:$vj), (v4i32 (SplatPat_simm5 simm5:$imm))),
1350 def : Pat<(OpNode (v4i32 LSX128:$vj), (v4i32 (SplatPat_uimm5 uimm5:$imm))),
1361 def : Pat<(OpNode (v4i32 LSX128:$vd), (v4i32 LSX128:$vj), (v4i32 LSX128:$vk)),
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp307 if (ST->useSLMArithCosts() && LT.second == MVT::v4i32) { in getArithmeticInstrCost()
467 { ISD::SHL, MVT::v4i32, { 1, 1, 1, 1 } }, // pslld in getArithmeticInstrCost()
468 { ISD::SRL, MVT::v4i32, { 1, 1, 1, 1 } }, // psrld in getArithmeticInstrCost()
469 { ISD::SRA, MVT::v4i32, { 1, 1, 1, 1 } }, // psrad in getArithmeticInstrCost()
508 { ISD::SHL, MVT::v4i32, { 1, 2, 1, 1 } }, // pslld. in getArithmeticInstrCost()
509 { ISD::SRL, MVT::v4i32, { 1, 2, 1, 1 } }, // psrld. in getArithmeticInstrCost()
510 { ISD::SRA, MVT::v4i32, { 1, 2, 1, 1 } }, // psrad. in getArithmeticInstrCost()
545 { ISD::SHL, MVT::v4i32, { 1, 1, 1, 1 } }, // pslld in getArithmeticInstrCost()
546 { ISD::SRL, MVT::v4i32, { 1, 1, 1, 1 } }, // psrld. in getArithmeticInstrCost()
547 { ISD::SRA, MVT::v4i32, { 1, 1, 1, 1 } }, // psrad. in getArithmeticInstrCost()
[all …]
H A DX86InstrXOP.td127 defm VPROTD : xop3op<0x92, "vprotd", rotl, v4i32, SchedWriteVarVecShift.XMM>;
131 defm VPSHAD : xop3op<0x9A, "vpshad", X86vpsha, v4i32, SchedWriteVarVecShift.XMM>;
135 defm VPSHLD : xop3op<0x96, "vpshld", X86vpshl, v4i32, SchedWriteVarVecShift.XMM>;
159 defm VPROTD : xop3opimm<0xC2, "vprotd", X86vrotli, v4i32,
220 def : Pat<(v4i32 (add (mul (v4i32 VR128:$src1), (v4i32 VR128:$src2)),
221 (v4i32 VR128:$src3))),
223 def : Pat<(v2i64 (add (X86pmuldq (bc_v2i64 (X86PShufd (v4i32 VR128:$src1), (i8 -11))),
224 (bc_v2i64 (X86PShufd (v4i32 VR12
[all...]
H A DX86InstrSSE.td144 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
174 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
302 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
303 (VMOVSSrr (v4i32 (V_SET0)), VR128:$src)>;
312 (v4i32 (VMOVSSrr (v4i32 (V_SET0)),
313 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm)))), sub_xmm)>;
321 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
322 (MOVSSrr (v4i32 (V_SET0)), VR128:$src)>;
631 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
639 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrMVE.td290 def MVE_v8i16 : MVEVectorVTInfo<v8i16, v4i32, v8i1, v4i1, 0b01, "i", ?>;
291 def MVE_v4i32 : MVEVectorVTInfo<v4i32, v2i64, v4i1, v2i1, 0b10, "i", ?>;
298 def MVE_v8s16 : MVEVectorVTInfo<v8i16, v4i32, v8i1, v4i1, 0b01, "s", 0b0>;
299 def MVE_v4s32 : MVEVectorVTInfo<v4i32, v2i64, v4i1, v2i1, 0b10, "s", 0b0>;
302 def MVE_v8u16 : MVEVectorVTInfo<v8i16, v4i32, v8i1, v4i1, 0b01, "u", 0b1>;
303 def MVE_v4u32 : MVEVectorVTInfo<v4i32, v2i64, v4i1, v2i1, 0b10, "u", 0b1>;
313 def MVE_v8p16 : MVEVectorVTInfo<v8i16, v4i32, v8i1, v4i1, 0b11, "p", 0b1>;
814 def : Pat<(ARMVADDLV (v4i32 MQPR:$vec)),
815 (InstN (v4i32 MQPR:$vec))>;
816 def : Pat<(ARMVADDLVA tGPREven:$acclo, tGPROdd:$acchi, (v4i32 MQPR:$vec)),
[all …]
H A DARMInstrNEON.td1074 def VLD1LNq32Pseudo : VLD1QLNPseudo<v4i32, load>;
1101 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
1410 def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32", v4i32, load,
2198 def VST1LNq32Pseudo : VST1QLNPseudo<v4i32, store, extractelt>;
2248 def VST1LNq32Pseudo_UPD : VST1QLNWBPseudo<v4i32, post_store, extractelt>;
3367 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
3370 [(set QPR:$Vd, (v4i32 (ARMvcmpz (v4i32 QPR:$Vm), fc)))]>;
3374 [(set QPR:$Vd, (v4i32 (ARMvcmpz (v4f32 QPR:$Vm), fc)))]> {
3434 def v4i32 : N3VQ_cmp<op24, op23, 0b10, op11_8, op4, itinQ32,
3436 v4i32, v4i32, fc, Commutable>;
[all …]
H A DARMTargetTransformInfo.cpp561 {ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0}, in getCastInstrCost()
562 {ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0}, in getCastInstrCost()
563 {ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 0}, in getCastInstrCost()
564 {ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 0}, in getCastInstrCost()
598 {ISD::TRUNCATE, MVT::v4i32, MVT::v4i16, 0}, in getCastInstrCost()
599 {ISD::TRUNCATE, MVT::v4i32, MVT::v4i8, 0}, in getCastInstrCost()
630 { ISD::ADD, MVT::v4i32, MVT::v4i16, 0 }, in getCastInstrCost()
633 { ISD::SUB, MVT::v4i32, MVT::v4i16, 0 }, in getCastInstrCost()
636 { ISD::MUL, MVT::v4i32, MVT::v4i16, 0 }, in getCastInstrCost()
639 { ISD::SHL, MVT::v4i32, MVT::v4i16, 0 }, in getCastInstrCost()
[all …]
H A DARMCallingConv.td34 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
60 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
75 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
95 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
112 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
170 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
188 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
215 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
238 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyTargetTransformInfo.cpp109 (SrcVT == MVT::v4i16 && DstVT == MVT::v4i32) || in getCastInstrCost()
115 if ((SrcVT == MVT::v4i8 && DstVT == MVT::v4i32) || in getCastInstrCost()
126 {ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 1}, in getCastInstrCost()
127 {ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1}, in getCastInstrCost()
132 {ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 2}, in getCastInstrCost()
133 {ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 2}, in getCastInstrCost()
H A DWebAssemblyISelLowering.cpp66 addRegisterClass(MVT::v4i32, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
91 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64, in WebAssemblyTargetLowering()
165 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64}) in WebAssemblyTargetLowering()
221 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64}) in WebAssemblyTargetLowering()
225 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64, in WebAssemblyTargetLowering()
233 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64, in WebAssemblyTargetLowering()
241 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64, in WebAssemblyTargetLowering()
247 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64}) in WebAssemblyTargetLowering()
252 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64, in WebAssemblyTargetLowering()
260 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64, in WebAssemblyTargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkorDetails.td615 def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^FCM(EQ|LE|GE|GT|LT)(v2i64|v4i32)rz$")>;
626 def : InstRW<[FalkorWr_2VXVY_4cyc], (instregex "^FCVTZ(S|U)(v2i64|v4i32)(_shift)?$")>;
645 (instregex "^ML(A|S)(v16i8|v8i16|v4i32|v2i64)(_indexed)?$")>;
719 def : InstRW<[FalkorWr_2VXVY_6cyc], (instregex "^(SQR?SHRN|UQR?SHRN|SQR?SHRUN)(v8i8|v16i8|v4i16|v8i16|v2i32|v4i32)_shift?$")>;
722 def : InstRW<[FalkorWr_2VXVY_1cyc], (instregex "^ADD(v16i8|v8i16|v4i32|v2i64)$")>;
725 def : InstRW<[FalkorWr_2VXVY_1cyc], (instregex "^(BIC|ORR)(v8i16|v4i32)$")>;
726 def : InstRW<[FalkorWr_2VXVY_1cyc], (instregex "^(NEG|SUB)(v16i8|v8i16|v4i32|v2i64)$")>;
729 def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^(S|U)(ADDLP|HADD|HSUB|SHL)(v16i8|v2i64|v4i32|v8i16)(_v.*)?$")>;
730 def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^(S|U)SHLL(v16i8|v8i16|v4i32|v8i8|v4i16|v2i32)(_shift)?$")>;
731 def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^(S|U)SHR(v16i8|v8i16|v4i32|v2i6
[all...]
H A DAArch64InstrInfo.td519 def SDT_AArch64ldnp : SDTypeProfile<2, 1, [SDTCisVT<0, v4i32>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>;
522 def SDT_AArch64stnp : SDTypeProfile<0, 3, [SDTCisVT<0, v4i32>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>;
1653 …def : Pat<(v4i32 (partial_reduce_umla (v4i32 V128:$Acc), (v16i8 V128:$MulLHS), (v16i8 V128:$MulRHS…
1654 (v4i32 (UDOTv16i8 V128:$Acc, V128:$MulLHS, V128:$MulRHS))>;
1655 …def : Pat<(v4i32 (partial_reduce_smla (v4i32 V128:$Acc), (v16i8 V128:$MulLHS), (v16i8 V128:$MulRHS…
1656 (v4i32 (SDOTv16i8 V128:$Acc, V128:$MulLHS, V128:$MulRHS))>;
1686 (v4i32 (bitconvert
1720 (AArch64duplane32 (v4i32 V128:$Rm),
1727 def v16i8 : BaseSIMDSUDOTIndex<1, ".4s", ".16b", ".4b", V128, v4i32, v16i8>;
1734 def : Pat<(v4i32 (partial_reduce_sumla v4i32:$Acc, v16i8:$LHS, v16i8:$RHS)),
[all …]
H A DAArch64SchedKryoDetails.td26 (instregex "(S|U)R?SRA(v2i64|v4i32|v8i16|v16i8)_shift")>;
39 (instregex "(S|U)ABA(v16i8|v8i16|v4i32)")>;
51 (instregex "(S|U)(ABD|QSUB|RHADD)(v16i8|v8i16|v4i32|v2i64)")>;
75 (instregex "(S|U)ADALP(v16i8|v8i16|v4i32)_v.*")>;
93 (instregex "((S|U)ADDLP|ABS)(v2i64|v4i32|v8i16|v16i8)(_v.*)?")>;
153 (instregex "(S|U)CVTF(v2i64|v4i32|v2f64|v4f32)(_shift)?")>;
165 (instregex "(S|U)H(ADD|SUB)(v16i8|v8i16|v4i32)")>;
207 (instregex "^(S|U)QADD(v16i8|v8i16|v4i32|v2i64)")>;
225 (instregex "(S|U)(QSHLU?|RSHR)(v16i8|v8i16|v4i32|v2i64)_shift$")>;
237 (instregex "(S|U)(QSHL|RSHL|QRSHL)(v16i8|v8i16|v4i32|v2i64)$")>;
[all …]
H A DAArch64SchedA57.td351 // Q form - v16i8, v8i16, v4i32
353 // Q form - v16i8, v8i16, v4i32, v2i64
364 def : InstRW<[A57Write_5cyc_2X_NonMul_Forward, A57ReadIVA3], (instregex "^[SU]ABA(v16i8|v8i16|v4i32)$")>;
371 def : InstRW<[A57Write_7cyc_1V_1X], (instregex "^[SU]?ADDL?V(v8i16|v4i32)v$")>;
376 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU](MIN|MAX)V(v4i16|v4i32)v$")>;
390 def : InstRW<[A57Write_6cyc_2W_Mul_Forward], (instregex "^MUL(v16i8|v8i16|v4i32)(_indexed)?$")>;
392 def : InstRW<[A57Write_6cyc_2W], (instregex "^(PMUL|SQR?DMULH)(v16i8|v8i16|v4i32)(_indexed)?$")>;
401 def : InstRW<[A57Write_6cyc_2W_Mul_Forward, A57ReadIVMA4], (instregex "^ML[AS](v16i8|v8i16|v4i32)(_indexed)?$")>;
425 def : InstRW<[A57Write_4cyc_2X], (instregex "^[SU]SHL(v16i8|v8i16|v4i32|v2i64)")>;
431 def : InstRW<[A57Write_5cyc_2X], (instregex "^[SU][QR]{1,2}SHL(v16i8|v8i16|v4i32|v2i6
[all...]
H A DAArch64InstrFormats.td165 BinOpFrag<(extract_subvector (v4i32 (AArch64duplane32 (v4i32 node:$LHS), node:$RHS)), (i64 2))>;
173 … [(v2i32 (extract_subvector (v4i32 (AArch64duplane32 (v4i32 node:$LHS), node:$RHS)), (i64 0))),
174 (v2i32 (AArch64duplane32 (v4i32 node:$LHS), node:$RHS))]>;
5524 def : Pat<(f16 (node (i32 (extractelt (v4i32 V128:$Rn), (i64 0))))),
5526 def : Pat<(f64 (node (i32 (extractelt (v4i32 V128:$Rn), (i64 0))))),
6222 def : Pat<(v4i32 (OpNode (v4i32 V128:$LHS), (v4i32 V128:$MHS),
6223 (v4i32 V128:$RHS))),
6250 def v4i32 : BaseSIMDThreeSameVector<1, U, 0b101, opc, V128,
6252 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
6276 def v4i32 : BaseSIMDThreeSameVector<1, U, 0b101, opc, V128,
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DBUFInstructions.td522 (load_vt (ld (MUBUFOffset v4i32:$srsrc, i32:$soffset, i32:$offset))),
523 (load_vt (inst v4i32:$srsrc, i32:$soffset, i32:$offset))
529 (load_vt (ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, i32:$offset))),
530 (load_vt (inst i64:$vaddr, v4i32:$srsrc, i32:$soffset, i32:$offset))
616 (st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset, i32:$offset)),
617 …(!cast<MUBUF_Pseudo>(BaseInst # _OFFSET) store_vt:$vdata, v4i32:$srsrc, i32:$soffset, i32:$offset)…
620 (st store_vt:$vdata, (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, i32:$offset)),
621 …(!cast<MUBUF_Pseudo>(BaseInst # _ADDR64) store_vt:$vdata, i64:$vaddr, v4i32:$srsrc, i32:$soffset, …
804 (atomic (MUBUFOffset v4i32:$srsrc, i32:$soffset, i32:$offset),
810 (atomic (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, i32:$offset),
[all …]
H A DCaymanInstructions.td84 def RAT_STORE_DWORD128 : RAT_STORE_DWORD <R600_Reg128, v4i32, 0xf>;
189 def : R600Pat<(v4i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)),
203 def : R600Pat<(v4i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)),
217 def : R600Pat<(v4i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)),
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZCallingConv.td61 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
81 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
127 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
134 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
139 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
201 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
239 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
262 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
265 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
286 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsMSAInstrInfo.td96 (v4i32 (vector_insert node:$vec, node:$val, node:$idx))>;
105 (v4i32 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>;
114 def vfseteq_v4f32 : vfsetcc_type<v4i32, v4f32, SETEQ>;
116 def vfsetge_v4f32 : vfsetcc_type<v4i32, v4f32, SETGE>;
118 def vfsetgt_v4f32 : vfsetcc_type<v4i32, v4f32, SETGT>;
120 def vfsetle_v4f32 : vfsetcc_type<v4i32, v4f32, SETLE>;
122 def vfsetlt_v4f32 : vfsetcc_type<v4i32, v4f32, SETLT>;
124 def vfsetne_v4f32 : vfsetcc_type<v4i32, v4f32, SETNE>;
126 def vfsetoeq_v4f32 : vfsetcc_type<v4i32, v4f32, SETOEQ>;
128 def vfsetoge_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGE>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/Utils/
H A DWebAssemblyTypeUtilities.cpp32 .Case("v4i32", MVT::v4i32) in parseMVT()
52 case MVT::v4i32: in toValType()

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