Lines Matching refs:v4i32
434 def SDT_AArch64ldnp : SDTypeProfile<2, 1, [SDTCisVT<0, v4i32>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>;
437 def SDT_AArch64stnp : SDTypeProfile<0, 3, [SDTCisVT<0, v4i32>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>;
1386 (v4i32 (bitconvert
1422 (AArch64duplane32 (v4i32 V128:$Rm),
1429 def v16i8 : BaseSIMDSUDOTIndex<1, ".4s", ".16b", ".4b", V128, v4i32, v16i8>;
1472 def : SHA3_pattern<EOR3, int_aarch64_crypto_eor3u, v4i32>;
1481 def : EOR3_pattern<v4i32>;
1490 def : BCAX_pattern<v4i32>;
1495 def : SHA3_pattern<BCAX, int_aarch64_crypto_bcaxu, v4i32>;
1500 def : SHA3_pattern<EOR3, int_aarch64_crypto_eor3s, v4i32>;
1505 def : SHA3_pattern<BCAX, int_aarch64_crypto_bcaxs, v4i32>;
1530 def : Pat<(v4i32 (int_aarch64_crypto_sm3ss1 (v4i32 V128:$Vn), (v4i32 V128:$Vm), (v4i32 V128:$Va))),
1531 (SM3SS1 (v4i32 V128:$Vn), (v4i32 V128:$Vm), (v4i32 V128:$Va))>;
1534 : Pat<(v4i32 (OpNode (v4i32 V128:$Vd), (v4i32 V128:$Vn), (v4i32 V128:$Vm))),
1535 (INST (v4i32 V128:$Vd), (v4i32 V128:$Vn), (v4i32 V128:$Vm))>;
1538 …: Pat<(v4i32 (OpNode (v4i32 V128:$Vd), (v4i32 V128:$Vn), (v4i32 V128:$Vm), (i64 VectorIndexS_timm:…
1539 (INST (v4i32 V128:$Vd), (v4i32 V128:$Vn), (v4i32 V128:$Vm), (VectorIndexS_timm:$imm))>;
1542 : Pat<(v4i32 (OpNode (v4i32 V128:$Vn), (v4i32 V128:$Vm))),
1543 (INST (v4i32 V128:$Vn), (v4i32 V128:$Vm))>;
1625 … (v4f16 (bitconvert (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexD:$idx))))>;
1627 … (v8f16 (bitconvert (v4i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))>;
3337 defm : ScalToVecROLoadPat<ro32, load, i32, v4i32, LDRSroW, LDRSroX, ssub>;
3388 defm : VecROLoadPat<ro128, v4i32, LDRQroW, LDRQroX>;
3505 def : Pat <(v4i32 (scalar_to_vector (i32
3507 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
3549 def : Pat<(v4i32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
3740 def : Pat<(v4i32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
3920 defm : LoadInsertZeroPatterns<load, v4i32, v2i32, nxv4i32, i32, LDRSui, LDURSi,
4141 defm : VecROStorePat<ro128, v4i32, FPR128, STRQroW, STRQroX>;
4171 defm : VecROStoreLane0Pat<ro32, store, v4i32, i32, i32, ssub, STRSroW, STRSroX>;
4266 def : Pat<(store (v4i32 FPR128:$Rt),
4307 defm : VecStoreLane0Pat<am_indexed32, store, v4i32, i32, i32, ssub, uimm12s4, STRSui>;
4416 def : Pat<(store (v4i32 FPR128:$Rt),
4454 defm : VecStoreULane0Pat<store, v4i32, i32, i32, ssub, STURSi>;
4537 def : Pat<(pre_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
4598 def : Pat<(post_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
5202 def : Pat<(abs (v4i32 (sub (zext (v4i16 V64:$opA)),
5205 def : Pat<(abs (v4i32 (sub (zext (extract_high_v8i16 (v8i16 V128:$opA))),
5211 def : Pat<(abs (v2i64 (sub (zext (extract_high_v4i32 (v4i32 V128:$opA))),
5212 (zext (extract_high_v4i32 (v4i32 V128:$opB)))))),
5236 def : Pat<(v4i32 (AArch64vashr (v4i32 V128:$Rn), (i32 31))),
5298 def : Pat<(v4i32 (to_int_sat v4f32:$Rn, i32)),
5309 def : Pat<(v4i32 (int_aarch64_neon_fcvtzs v4f32:$Rn)), (FCVTZSv4f32 $Rn)>;
5315 def : Pat<(v4i32 (int_aarch64_neon_fcvtzu v4f32:$Rn)), (FCVTZUv4f32 $Rn)>;
5351 def : Pat<(vnot (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
5398 def : Pat<(AArch64vshl (v4i32 (ext (v4i16 V64:$Rn))), (i32 16)),
5400 def : Pat<(AArch64vshl (v4i32 (ext (extract_high_v8i16 (v8i16 V128:$Rn)))), (i32 16)),
5404 def : Pat<(AArch64vshl (v2i64 (ext (extract_high_v4i32 (v4i32 V128:$Rn)))), (i32 32)),
5424 def : Pat<(v4i16 (trunc (umin (v4i32 V128:$Vn), (v4i32 VImmFFFF)))),
5436 def : Pat<(v4i16 (trunc (smin (smax (v4i32 V128:$Vn), (v4i32 VImm8000)),
5437 (v4i32 VImm7FFF)))),
5439 def : Pat<(v4i16 (trunc (smax (smin (v4i32 V128:$Vn), (v4i32 VImm7FFF)),
5440 (v4i32 VImm8000)))),
5451 (v4i16 (trunc (umin (v4i32 V128:$Vn), (v4i32 VImmFFFF)))))),
5471 (v4i16 (trunc (smin (smax (v4i32 V128:$Vn), (v4i32 VImm8000)),
5472 (v4i32 VImm7FFF)))))),
5476 (v4i16 (trunc (smax (smin (v4i32 V128:$Vn), (v4i32 VImm7FFF)),
5477 (v4i32 VImm8000)))))),
5487 def : Pat<(v4i32 (bswap (v4i32 V128:$Rn))),
5488 (v4i32 (REV32v16i8 (v4i32 V128:$Rn)))>;
5504 foreach VT = [ v8i8, v16i8, v4i16, v8i16, v2i32, v4i32, v2i64 ] in {
5627 def : Pat<(AArch64bsp (v4i32 V128:$Rd), V128:$Rn, V128:$Rm),
5644 def : Pat<(v4i32 (InFrag (v4i32 V128:$Rn), (v4i32 V128:$Rm))),
5645 (v4i32 (!cast<Instruction>(INST # v4i32) (v4i32 V128:$Rn), (v4i32 V128:$Rm)))>;
5667 def : Pat<(v4i32 (InFrag (v4i32 V128:$Rn), (v4i32 V128:$Rm))),
5668 (v4i32 (!cast<Instruction>(INST # v4i32) (v4i32 V128:$Rm), (v4i32 V128:$Rn)))>;
5689 def : Pat<(v4i32 (InFrag (v4i32 V128:$Rn), immAllZerosV)),
5690 (v4i32 (!cast<Instruction>(INST # v4i32rz) (v4i32 V128:$Rn)))>;
5712 def : Pat<(v4i32 (InFrag immAllZerosV, (v4i32 V128:$Rn))),
5713 (v4i32 (!cast<Instruction>(INST # v4i32rz) (v4i32 V128:$Rn)))>;
6178 def : Pat<(f32 (sint_to_fp (i32 (vector_extract (v4i32 FPR128:$Rn), (i64 0))))),
6179 (SCVTFv1i32 (i32 (EXTRACT_SUBREG (v4i32 FPR128:$Rn), ssub)))>;
6181 def : Pat<(f32 (uint_to_fp (i32 (vector_extract (v4i32 FPR128:$Rn), (i64 0))))),
6182 (UCVTFv1i32 (i32 (EXTRACT_SUBREG (v4i32 FPR128:$Rn), ssub)))>;
6355 (EXTRACT_SUBREG (v4i32 (INST4H
6356 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), V64:$Ra, dsub),
6384 … (EXTRACT_SUBREG (v4i32 (!cast<Instruction>(Inst#"Lv4i16_v4i32") V64:$Rn, V64:$Rm)), dsub)>;
6394 …(EXTRACT_SUBREG (v4i32 (!cast<Instruction>(Inst#"Wv4i16_v4i32") (INSERT_SUBREG (v4i32 (IMPLICIT_DE…
6414 def : Pat<(v4i16 (trunc (v4i32 (AArch64vlshr (add V128:$Rn, V128:$Rm),
6426 (trunc (v4i32 (AArch64vlshr (add V128:$Rn, V128:$Rm),
6439 def : Pat<(v4i16 (trunc (v4i32 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
6451 (trunc (v4i32 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
6503 defm : ExtPat<v2i32, v4i32, 2>;
6532 def : concat_trunc_to_uzp1_pat<v4i32, v4i16, v8i16>;
6533 def : concat_trunc_to_uzp1_pat<v2i64, v2i32, v4i32>;
6545 def : trunc_concat_trunc_to_xtn_uzp1_pat<v4i32, v4i16, v8i16, v8i8>;
6546 def : trunc_concat_trunc_to_xtn_uzp1_pat<v2i64, v2i32, v4i32, v4i16>;
6558 (v4i16 (trunc (AArch64vlshr (v4i32 V128:$Vn), (i32 16)))),
6559 (v4i16 (trunc (AArch64vlshr (v4i32 V128:$Vm), (i32 16)))))),
6561 def : Pat<(v4i32 (concat_vectors
6668 def DUPv4i32gpr : SIMDDupFromMain<1, {?,?,1,0,0}, ".4s", v4i32, V128, GPR32>;
6673 def DUPv4i32lane : SIMDDup32FromElement<1, ".4s", v4i32, V128>;
6687 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
6691 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
6695 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rn, dsub),
6757 defm : DUPWithTruncPats<v8i8, v2i32, v4i32, i32, DUPv8i8lane, VecIndex_x4>;
6758 defm : DUPWithTruncPats<v4i16, v2i32, v4i32, i32, DUPv4i16lane, VecIndex_x2>;
6761 defm : DUPWithTruncPats<v16i8, v2i32, v4i32, i32, DUPv16i8lane, VecIndex_x4>;
6762 defm : DUPWithTruncPats<v8i16, v2i32, v4i32, i32, DUPv8i16lane, VecIndex_x2>;
6781 defm : DUPWithTrunci64Pats<v4i32, DUPv4i32lane, VecIndex_x2>;
6797 def : Pat<(sext (i32 (vector_extract (v4i32 V128:$Rn), VectorIndexS:$idx))),
6858 def : Pat<(v4i32 (scalar_to_vector (i32 FPR32:$Rn))),
6859 (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
6953 (INSvi32gpr (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), V64:$Rn, dsub)),
6992 def : Pat<(v4i32 (int_aarch64_neon_vcopy_lane
6993 (v4i32 V128:$Vd), VectorIndexS:$idx, (v4i32 V128:$Vs),
6995 (v4i32 (INSvi32lane
7041 defm : Neon_INS_elt_pattern<v4i32, v2i32, i32, INSvi32lane>;
7046 def : Pat<(v4i32 (vector_insert v4i32:$src, (i32 (bitconvert (f32 FPR32:$Sn))), (i64 imm:$Immd))),
7050 (INSvi32lane (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), V64:$src, dsub)),
7057 // f32 bitcast(vector_extract(v4i32 src, lane)) -> EXTRACT_SUBREG(INSvi32lane(-, 0, src, lane))
7058 def : Pat<(f32 (bitconvert (i32 (vector_extract v4i32:$src, imm:$Immd)))),
7060 def : Pat<(f32 (bitconvert (i32 (vector_extract v4i32:$src, (i64 0))))),
7109 defm : ConcatPat<v4i32, v2i32>;
7142 def : Pat<(v4i32 (AArch64uaddv (v4i32 (addlp (v8i16 V128:$op))))),
7143 … (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), (!cast<Instruction>(Opc#"v8i16v") V128:$op), ssub)>;
7148 def : Pat<(v2i64 (AArch64uaddv (v2i64 (addlp (v4i32 V128:$op))))),
7162 def : Pat<(i32 (vecreduce_add (v4i32 (addlp (v8i16 V128:$Rn))))),
7168 def : Pat<(i64 (vecreduce_add (v2i64 (addlp (v4i32 V128:$Rn))))),
7176 def : Pat<(i64 (int_aarch64_neon_uaddlv (v4i32 (AArch64uaddlp (v8i16 V128:$op))))),
7178 (v4i32 (SUBREG_TO_REG (i64 0), (UADDLVv8i16v V128:$op), ssub)),
7186 def : Pat<(v2i64 (AArch64uaddlv (v4i32 (AArch64uaddlp (v8i16 V128:$op))))),
7189 def : Pat<(v4i32 (AArch64uaddlv (v8i16 (AArch64uaddlp (v16i8 V128:$op))))),
7190 (v4i32 (SUBREG_TO_REG (i64 0), (UADDLVv16i8v V128:$op), hsub))>;
7192 def : Pat<(v4i32 (AArch64uaddlv (v4i16 (AArch64uaddlp (v8i8 V64:$op))))),
7193 (v4i32 (SUBREG_TO_REG (i64 0), (UADDLVv8i8v V64:$op), hsub))>;
7196 def : Pat<(v4i32 (addlv (v8i8 V64:$Rn))),
7197 (v4i32 (SUBREG_TO_REG (i64 0), (!cast<Instruction>(Opc#"v8i8v") V64:$Rn), hsub))>;
7199 def : Pat<(v4i32 (addlv (v4i16 V64:$Rn))),
7200 (v4i32 (SUBREG_TO_REG (i64 0), (!cast<Instruction>(Opc#"v4i16v") V64:$Rn), ssub))>;
7202 def : Pat<(v4i32 (addlv (v16i8 V128:$Rn))),
7203 (v4i32 (SUBREG_TO_REG (i64 0), (!cast<Instruction>(Opc#"v16i8v") V128:$Rn), hsub))>;
7205 def : Pat<(v4i32 (addlv (v8i16 V128:$Rn))),
7206 (v4i32 (SUBREG_TO_REG (i64 0), (!cast<Instruction>(Opc#"v8i16v") V128:$Rn), ssub))>;
7208 def : Pat<(v2i64 (addlv (v4i32 V128:$Rn))),
7234 def : Pat<(v4i32 (opNode V128:$Rn)),
7235 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
7258 def : Pat<(i32 (vector_extract (v4i32 (opNode V128:$Rn)), (i64 0))),
7259 (EXTRACT_SUBREG (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
7338 def : Pat<(i32 (vecreduce_add (v4i32 V128:$Rn))),
7385 def : Pat<(i32 (opNode (v4i32 V128:$Rn))),
7429 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
7460 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
7555 def : Pat<(v4i32 immAllZerosV), (MOVIv2d_ns (i32 0))>;
7564 def : Pat<(v4i32 immAllOnesV), (MOVIv2d_ns (i32 255))>;
7610 def : Pat<(v4i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
7623 [(set (v4i32 V128:$Rd),
7656 def : Pat<(v4i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
7669 [(set (v4i32 V128:$Rd),
7787 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
7791 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
7795 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rm, dsub),
7834 (vector_extract (v4i32 V128:$Vm),
7973 def : Pat<(v4f32 (sint_to_fp (v4i32 (AArch64vashr_exact v4i32:$Vn, i32:$shift)))),
7995 def : SHLToADDPat<v4i32, FPR128>;
8050 def VImm0000000080000000: PatLeaf<(AArch64NvCast (v2f64 (fneg (AArch64NvCast (v4i32 (AArch64movi_sh…
8055 def : Pat<(v4i16 (trunc (AArch64vlshr (add (v4i32 V128:$Vn), VImm00008000), (i32 16)))),
8056 (RADDHNv4i32_v4i16 V128:$Vn, (v4i32 (MOVIv2d_ns (i32 0))))>;
8062 def : Pat<(v4i16 (int_aarch64_neon_rshrn (v4i32 V128:$Vn), (i32 16))),
8063 (RADDHNv4i32_v4i16 V128:$Vn, (v4i32 (MOVIv2d_ns (i32 0))))>;
8076 (v4i16 (trunc (AArch64vlshr (add (v4i32 V128:$Vn), VImm00008000), (i32 16)))))),
8079 (v4i32 (MOVIv2d_ns (i32 0))))>;
8081 def : Pat<(v4i32 (concat_vectors
8095 (v4i16 (int_aarch64_neon_rshrn (v4i32 V128:$Vn), (i32 16))))),
8098 (v4i32 (MOVIv2d_ns (i32 0))))>;
8099 def : Pat<(v4i32 (concat_vectors
8111 def : Pat<(v4i16 (trunc (AArch64vlshr (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))),
8122 (trunc (AArch64vlshr (v4i32 V128:$Rn),
8126 def : Pat<(v4i32 (concat_vectors (v2i32 V64:$Rd),
8137 def : Pat<(v4i32 (sext (v4i16 V64:$Rn))), (SSHLLv4i16_shift V64:$Rn, (i32 0))>;
8138 def : Pat<(v4i32 (zext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
8139 def : Pat<(v4i32 (anyext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
8152 def : Pat<(v4i32 (anyext (v4i16 (extract_high_v8i16 (v8i16 V128:$Rn)) ))),
8154 def : Pat<(v4i32 (zext (v4i16 (extract_high_v8i16 (v8i16 V128:$Rn)) ))),
8156 def : Pat<(v4i32 (sext (v4i16 (extract_high_v8i16 (v8i16 V128:$Rn)) ))),
8158 def : Pat<(v2i64 (anyext (v2i32 (extract_high_v4i32 (v4i32 V128:$Rn)) ))),
8160 def : Pat<(v2i64 (zext (v2i32 (extract_high_v4i32 (v4i32 V128:$Rn)) ))),
8162 def : Pat<(v2i64 (sext (v2i32 (extract_high_v4i32 (v4i32 V128:$Rn)) ))),
8394 def : Ld1Pat<v4i32, LD1Onev4s>;
8407 def : St1Pat<v4i32, ST1Onev4s>;
8451 def : Pat<(v4i32 (AArch64dup (i32 (load GPR64sp:$Rn)))),
8466 def : Pat<(v2i32 (AArch64duplane32 (v4i32 (insert_subvector undef, (v2i32 (load GPR64sp:$Rn)), (i64…
8468 def : Pat<(v4i32 (AArch64duplane32 (v4i32 (load GPR64sp:$Rn)), (i64 0))),
8499 def : Ld1Lane128Pat<load, VectorIndexS, v4i32, i32, LD1i32>;
8509 // (v4i32 (insert_vector_elt (load anyext from i8) idx))
8540 def : Ld1Lane128IdxOpPat<extloadi16, VectorIndexS, v4i32, i32, LD1i16, VectorIndexStoH>;
8541 def : Ld1Lane128IdxOpPat<extloadi8, VectorIndexS, v4i32, i32, LD1i8, VectorIndexStoB>;
8599 def : St1Lane128Pat<store, VectorIndexS, v4i32, i32, ST1i32>;
8666 defm : St1LanePost128Pat<post_store, VectorIndexS, v4i32, i32, ST1i32_POST, 4>;
8852 def : Pat<(v4i32 (mulhs V128:$Rn, V128:$Rm)),
8868 def : Pat<(v4i32 (mulhu V128:$Rn, V128:$Rm)),
8927 foreach VT = [ v16i8, v8i16, v8f16, v8bf16, v4i32, v4f32, v2i64, v2f64 ] in
8928 foreach VT2 = [ v16i8, v8i16, v8f16, v8bf16, v4i32, v4f32, v2i64, v2f64 ] in
9236 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))), (f128 FPR128:$src)>;
9247 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))),
9271 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))), (v2f64 FPR128:$src)>;
9282 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))),
9323 def : Pat<(v4f32 (bitconvert (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>;
9327 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>;
9338 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))),
9354 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))), (v4i32 FPR128:$src)>;
9355 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>;
9356 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>;
9357 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>;
9358 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>;
9359 def : Pat<(v4i32 (bitconvert (v8f16 FPR128:$src))), (v4i32 FPR128:$src)>;
9360 def : Pat<(v4i32 (bitconvert (v8bf16 FPR128:$src))), (v4i32 FPR128:$src)>;
9363 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))),
9364 (v4i32 (EXTv16i8 (REV64v4i32 FPR128:$src),
9367 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))),
9368 (v4i32 (REV64v4i32 FPR128:$src))>;
9369 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))),
9370 (v4i32 (REV32v8i16 FPR128:$src))>;
9371 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))),
9372 (v4i32 (REV32v16i8 FPR128:$src))>;
9373 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))),
9374 (v4i32 (REV64v4i32 FPR128:$src))>;
9375 def : Pat<(v4i32 (bitconvert (v8f16 FPR128:$src))),
9376 (v4i32 (REV32v8i16 FPR128:$src))>;
9377 def : Pat<(v4i32 (bitconvert (v8bf16 FPR128:$src))),
9378 (v4i32 (REV32v8i16 FPR128:$src))>;
9380 def : Pat<(v4i32 (bitconvert (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>;
9385 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>;
9397 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))),
9412 def : Pat<(v8f16 (bitconvert (v4i32 FPR128:$src))), (v8f16 FPR128:$src)>;
9419 def : Pat<(v8bf16 (bitconvert (v4i32 FPR128:$src))), (v8bf16 FPR128:$src)>;
9431 def : Pat<(v8f16 (bitconvert (v4i32 FPR128:$src))),
9446 def : Pat<(v8bf16 (bitconvert (v4i32 FPR128:$src))),
9461 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>;
9475 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))),
9510 def : Pat<(v2i32 (extract_subvector (v4i32 FPR128:$Rn), (i64 1))),
9523 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
9559 def : Pat<(AArch64addp (v2i32 (extract_subvector (v4i32 FPR128:$Rn), (i64 0))),
9560 (v2i32 (extract_subvector (v4i32 FPR128:$Rn), (i64 2)))),
9580 def : Pat<(v4i32 (add (AArch64uzp1 (v4i32 FPR128:$Rn), (v4i32 FPR128:$Rm)),
9581 (AArch64uzp2 (v4i32 FPR128:$Rn), (v4i32 FPR128:$Rm)))),
9582 (v4i32 (ADDPv4i32 $Rn, $Rm))>;
9624 def : NTStore128Pat<v4i32>;
9701 def : Pat<(i32 (extractelt (v4i32 V128:$V), (i64 0))), (EXTRACT_SUBREG V128:$V, ssub)>;
9744 (v4i32 (AArch64uaddv
9776 (v4i32
9783 (v4i32 (AArch64uaddv