Lines Matching refs:v4i32
161 BinOpFrag<(extract_subvector (v4i32 (AArch64duplane32 (v4i32 node:$LHS), node:$RHS)), (i64 2))>;
169 … [(v2i32 (extract_subvector (v4i32 (AArch64duplane32 (v4i32 node:$LHS), node:$RHS)), (i64 0))),
170 (v2i32 (AArch64duplane32 (v4i32 node:$LHS), node:$RHS))]>;
5848 def : Pat<(v4i32 (OpNode (v4i32 V128:$LHS), (v4i32 V128:$MHS),
5849 (v4i32 V128:$RHS))),
5876 def v4i32 : BaseSIMDThreeSameVector<1, U, 0b101, opc, V128,
5878 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
5896 def : Pat<(v4i32 (OpNode V128:$LHS, V128:$RHS)),
5897 (!cast<Instruction>(inst#"v4i32") V128:$LHS, V128:$RHS)>;
5920 def v4i32 : BaseSIMDThreeSameVector<1, U, 0b101, opc, V128,
5922 [(set V128:$Rd, (v4i32 (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm))))]>;
5947 def v4i32 : BaseSIMDThreeSameVectorTied<1, U, 0b101, opc, V128,
5949 [(set (v4i32 V128:$dst),
5950 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
6005 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
6051 def v4i32 : BaseSIMDThreeSameVector<1, U, 0b101, opc, V128,
6053 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
6075 def : Pat<(v4i32 (OpNode V128:$LHS, V128:$RHS)),
6110 def : Pat<(v4i32 (OpNode (v4i32 V128:$LHS), (v4i32 V128:$MHS),
6111 (v4i32 V128:$RHS))),
6138 v4i32, v16i8, OpNode>;
6305 def v4i32 : BaseSIMDTwoSameVector<1, U, 0b10, opc, 0b00, V128,
6307 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
6340 def v4i32 : BaseSIMDVectorLShiftLongBySize<1, 0b10, V128,
6359 [(set (v4i32 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
6365 [(set (v2i64 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
6384 [(set (v4i32 V128:$dst), (OpNode (v4i32 V128:$Rd),
6393 (v4i32 V128:$Rn)))]>;
6414 def v4i32 : BaseSIMDTwoSameVectorTied<1, U, 0b10, opc, 0b00, V128,
6416 [(set (v4i32 V128:$dst), (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn)))]>;
6439 def v4i32 : BaseSIMDTwoSameVector<1, U, 0b10, opc, 0b00, V128,
6441 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
6533 def v4i32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, 0b00, V128,
6535 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
6554 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn)))]>;
6576 [(set (v4f32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
6637 [(set (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
6643 def v4i32 : BaseSIMDMixedTwoVectorTied<1, U, 0b10, opc, V128, V128,
6649 def : Pat<(concat_vectors (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn))),
6653 (!cast<Instruction>(NAME # "v4i32")
6712 v4i32, v4i32, OpNode>;
6736 v4i32, v4f32, OpNode>;
6819 def v4i32 : BaseSIMDFPCvtTwoVector<1, U, {S,1}, opc, V128, V128,
6830 def v4i32 : BaseSIMDFPCvtTwoVectorTied<1, U, {S,1}, opc, V128, V128,
6920 [(set (v4i16 V64:$Rd), (IntOp (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
6942 def : Pat<(concat_vectors (v4i16 V64:$Rd), (IntOp (v4i32 V128:$Rn),
6943 (v4i32 V128:$Rm))),
6985 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
6989 [(set (v4i32 V128:$Rd), (OpNode (extract_high_v8i16 (v8i16 V128:$Rn)),
6998 [(set (v2i64 V128:$Rd), (OpNode (extract_high_v4i32 (v4i32 V128:$Rn)),
6999 (extract_high_v4i32 (v4i32 V128:$Rm))))]>;
7018 [(set (v4i32 V128:$Rd),
7023 [(set (v4i32 V128:$Rd),
7035 (zext (v2i32 (OpNode (extract_high_v4i32 (v4i32 V128:$Rn)),
7036 (extract_high_v4i32 (v4i32 V128:$Rm))))))]>;
7058 [(set (v4i32 V128:$dst),
7059 (add (v4i32 V128:$Rd),
7064 [(set (v4i32 V128:$dst),
7065 (add (v4i32 V128:$Rd),
7079 (zext (v2i32 (OpNode (extract_high_v4i32 (v4i32 V128:$Rn)),
7080 (extract_high_v4i32 (v4i32 V128:$Rm)))))))]>;
7097 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
7101 [(set (v4i32 V128:$Rd), (OpNode (extract_high_v8i16 (v8i16 V128:$Rn)),
7110 [(set (v2i64 V128:$Rd), (OpNode (extract_high_v4i32 (v4i32 V128:$Rn)),
7111 (extract_high_v4i32 (v4i32 V128:$Rm))))]>;
7132 [(set (v4i32 V128:$dst),
7133 (OpNode (v4i32 V128:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
7137 [(set (v4i32 V128:$dst),
7138 (OpNode (v4i32 V128:$Rd),
7151 (extract_high_v4i32 (v4i32 V128:$Rn)),
7152 (extract_high_v4i32 (v4i32 V128:$Rm))))]>;
7160 [(set (v4i32 V128:$dst),
7161 (Accum (v4i32 V128:$Rd),
7162 (v4i32 (int_aarch64_neon_sqdmull (v4i16 V64:$Rn),
7167 [(set (v4i32 V128:$dst),
7168 (Accum (v4i32 V128:$Rd),
7169 (v4i32 (int_aarch64_neon_sqdmull (extract_high_v8i16 (v8i16 V128:$Rn)),
7183 (v2i64 (int_aarch64_neon_sqdmull (extract_high_v4i32 (v4i32 V128:$Rn)),
7184 (extract_high_v4i32 (v4i32 V128:$Rm))))))]>;
7201 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i16 V64:$Rm)))]>;
7205 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
7215 (extract_high_v4i32 (v4i32 V128:$Rm))))]>;
7292 def v4i32 : BaseSIMDZipVector<0b101, opc, V128,
7293 asm, ".4s", OpNode, v4i32>;
7308 (!cast<Instruction>(NAME#"v4i32") V128:$Rn, V128:$Rm)>;
7834 : SIMDDupFromElement<Q, size, ".s", vectype, v4i32, vecreg,
7938 def vi32_idx0 : SIMDUMov<0, ".s", v4i32, GPR32, VectorIndex0> {
7961 def vi32 : SIMDUMov<0, ".s", v4i32, GPR32, VectorIndexS> {
8027 def vi32gpr : SIMDInsFromMain<".s", v4i32, GPR32, VectorIndexS> {
8053 def vi32lane : SIMDInsFromElement<".s", v4i32, i32, VectorIndexS> {
8452 def v4i32 : BaseSIMDModifiedImmVectorShift<1, op, w_cmode, V128,
8475 def v4i32 : BaseSIMDModifiedImmVectorShiftTied<1, op, w_cmode, V128,
8477 [(set (v4i32 V128:$dst), (OpNode V128:$Rd,
8736 [(set (v4i32 V128:$dst), (OpNode (v4i32 V128:$Rd),
8755 (AArch64duplane32 (v4i32 V128:$Rm),
8767 V128, v4i32, v16i8, OpNode>;
9137 (v2i32 V64:$Rn), (v4i32 V128:$Rm),
9142 def : Pat<(v4i32 (OpNodeLane
9143 (v4i32 V128:$Rn), (v2i32 V64:$Rm),
9149 def : Pat<(v4i32 (OpNodeLaneQ
9150 (v4i32 V128:$Rn),
9151 (v4i32 V128:$Rm),
9191 (dup_v4i32 (v4i32 V128:$Rm), VectorIndexS:$idx)))]> {
9201 [(set (v4i32 V128:$Rd),
9202 (OpNode (v4i32 V128:$Rn),
9203 (v4i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
9223 (i32 (vector_extract (v4i32 V128:$Rm),
9265 (dup_v4i32 (v4i32 V128:$Rm), VectorIndexS:$idx)))]> {
9275 [(set (v4i32 V128:$Rd),
9276 (OpNode (v4i32 V128:$Rn),
9277 (v4i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
9317 (dup_v4i32 (v4i32 V128:$Rm), VectorIndexS:$idx)))]> {
9327 [(set (v4i32 V128:$dst),
9328 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
9329 (v4i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
9342 [(set (v4i32 V128:$Rd),
9355 [(set (v4i32 V128:$Rd),
9371 (dup_v4i32 (v4i32 V128:$Rm), VectorIndexS:$idx)))]> {
9382 (OpNode (extract_high_v4i32 (v4i32 V128:$Rn)),
9383 (extract_high_dup_v4i32 (v4i32 V128:$Rm), VectorIndexS:$idx)))]> {
9413 [(set (v4i32 V128:$dst),
9414 (Accum (v4i32 V128:$Rd),
9415 (v4i32 (int_aarch64_neon_sqdmull
9429 [(set (v4i32 V128:$dst),
9430 (Accum (v4i32 V128:$Rd),
9431 (v4i32 (int_aarch64_neon_sqdmull
9448 (dup_v4i32 (v4i32 V128:$Rm), VectorIndexS:$idx)))))]> {
9461 (extract_high_v4i32 (v4i32 V128:$Rn)),
9462 (extract_high_dup_v4i32 (v4i32 V128:$Rm), VectorIndexS:$idx)))))]> {
9479 (v4i32 (int_aarch64_neon_sqdmull
9491 (v4i32 (int_aarch64_neon_sqdmull
9509 (i32 (vector_extract (v4i32 V128:$Rm),
9525 [(set (v4i32 V128:$Rd),
9538 [(set (v4i32 V128:$Rd),
9554 (dup_v4i32 (v4i32 V128:$Rm), VectorIndexS:$idx)))]> {
9565 (OpNode (extract_high_v4i32 (v4i32 V128:$Rn)),
9566 (extract_high_dup_v4i32 (v4i32 V128:$Rm), VectorIndexS:$idx)))]> {
9581 [(set (v4i32 V128:$dst),
9582 (OpNode (v4i32 V128:$Rd), (v4i16 V64:$Rn),
9594 [(set (v4i32 V128:$dst),
9595 (OpNode (v4i32 V128:$Rd),
9610 (dup_v4i32 (v4i32 V128:$Rm), VectorIndexS:$idx)))]> {
9622 (extract_high_v4i32 (v4i32 V128:$Rn)),
9623 (extract_high_dup_v4i32 (v4i32 V128:$Rm), VectorIndexS:$idx)))]> {
9892 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (i32 imm:$imm)))]> {
9937 [(set (v4f32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (i32 imm:$imm)))]> {
9972 [(set (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))]> {
10011 def : Pat<(concat_vectors (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn),
10073 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
10139 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
10205 [(set (v4i32 V128:$dst),
10206 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
10277 [(set (v4i32 V128:$dst),
10278 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
10315 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), vecshiftL16:$imm))]> {
10323 [(set (v4i32 V128:$Rd),
10341 (OpNode (extract_high_v4i32 (v4i32 V128:$Rn)), vecshiftL32:$imm))]> {
11220 def v4i32 : BaseSIMDThreeSameVectorTiedR0<1, U, 0b10, opc, V128, asm, ".4s",
11221 [(set (v4i32 V128:$dst),
11222 (v4i32 (op (v4i32 V128:$Rd), (v4i32 V128:$Rn), (v4i32 V128:$Rm))))]>;
11258 (dup_v4i32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
11267 [(set (v4i32 V128:$dst),
11268 (v4i32 (op (v4i32 V128:$Rd), (v4i32 V128:$Rn),
11269 (v4i32 (AArch64duplane32 (v4i32 V128:$Rm),
11291 (i32 (vector_extract (v4i32 V128:$Rm),
11588 [(set (v4i32 FPR128:$dst),
11589 (OpNode (v4i32 FPR128:$Rd), (i32 FPR32:$Rn),
11590 (v4i32 V128:$Rm)))]>;
11595 [(set (v4i32 V128:$dst),
11596 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
11597 (v4i32 V128:$Rm)))]>;
11602 [(set (v4i32 FPR128:$dst),
11603 (OpNode (v4i32 FPR128:$Rd), (v4i32 FPR128:$Rn),
11604 (v4i32 V128:$Rm)))]>;
11625 [(set (v4i32 V128:$dst),
11626 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn)))]>;