Lines Matching refs:v4i32
1074 def VLD1LNq32Pseudo : VLD1QLNPseudo<v4i32, load>;
1101 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
1410 def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32", v4i32, load,
2198 def VST1LNq32Pseudo : VST1QLNPseudo<v4i32, store, extractelt>;
2248 def VST1LNq32Pseudo_UPD : VST1QLNWBPseudo<v4i32, post_store, extractelt>;
3367 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
3370 [(set QPR:$Vd, (v4i32 (ARMvcmpz (v4i32 QPR:$Vm), fc)))]>;
3374 [(set QPR:$Vd, (v4i32 (ARMvcmpz (v4f32 QPR:$Vm), fc)))]> {
3434 def v4i32 : N3VQ_cmp<op24, op23, 0b10, op11_8, op4, itinQ32,
3436 v4i32, v4i32, fc, Commutable>;
3459 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3460 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
3475 v4i16, v4i32, OpNode>;
3492 v4i16, v4i32, IntOp>;
3505 def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
3506 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
3538 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
3540 v4i32, v4i32, OpNode, Commutable>;
3547 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, "i32",
3548 v4i32, v2i32, ShOp>;
3587 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, f, itinQ32,
3589 v4i32, v4i32, IntOp, Commutable>;
3608 def v4i32 : N3VQIntSh<op24, op23, 0b10, op11_8, op4, f, itinQ32,
3610 v4i32, v4i32, IntOp>;
3623 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
3624 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
3698 v4i16, v4i32, IntOp, Commutable>;
3714 def v4i32 : N3VL<op24, op23, 0b01, op11_8, op4, itin16,
3716 v4i32, v4i16, OpNode, Commutable>;
3726 !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
3738 def v4i32 : N3VLExt<op24, op23, 0b01, op11_8, op4, itin16,
3740 v4i32, v4i16, OpNode, ExtOp, Commutable>;
3753 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin16,
3755 v4i32, v4i16, IntOp, Commutable>;
3765 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
3789 def v4i32 : N3VLIntExt<op24, op23, 0b01, op11_8, op4, itin,
3791 v4i32, v4i16, IntOp, ExtOp, Commutable>;
3806 def v4i32 : N3VW<op24, op23, 0b01, op11_8, op4,
3808 v4i32, v4i16, OpNode, ExtOp, Commutable>;
3834 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
3835 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
3849 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
3850 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
3873 def v4i32 : N3VQIntOp<op24, op23, 0b10, op11_8, op4, itinQ,
3874 OpcodeStr, !strconcat(Dt, "32"), v4i32, IntOp, OpNode>;
3892 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, itinQ32,
3893 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
3919 def v4i32 : N3VLMulOp<op24, op23, 0b01, op11_8, op4, itin16, OpcodeStr,
3920 !strconcat(Dt, "16"), v4i32, v4i16, MulOp, OpNode>;
3928 !strconcat(Dt,"16"), v4i32, v4i16, MulOp, OpNode>;
3940 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, itin16,
3941 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
3949 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
3970 def v4i32 : N3VLIntExtOp<op24, op23, 0b01, op11_8, op4, itin,
3971 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16,
3996 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3997 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3998 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
4019 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
4020 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
4021 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
4057 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
4058 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
4094 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
4095 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
4133 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
4134 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
4173 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
4174 N2RegVShLFrm, OpcodeStr, "32", v4i32, NEONvsliImm> {
4209 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm32,
4210 N2RegVShRFrm, OpcodeStr, "32", v4i32, NEONvsriImm> {
4227 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
4228 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, imm1_15, OpNode> {
4249 v4i16, v4i32, shr_imm16, OpNode> {
4316 def : Pat<(v4i16 (trunc (ARMvshruImm (add (v4i32 QPR:$Vn), QPR:$Vm), 16))),
4358 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
4359 (v4i32 (ARMvduplane (v4i32 QPR:$src2), imm:$lane)))),
4360 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
4411 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
4412 (v4i32 (ARMvduplane (v4i32 QPR:$src2),
4414 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
4436 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
4437 (v4i32 (ARMvduplane (v4i32 QPR:$src2),
4439 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
4508 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
4509 (mul (v4i32 QPR:$src2),
4510 (v4i32 (ARMvduplane (v4i32 QPR:$src3), imm:$lane))))),
4511 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
4552 def : Pat<(v4i32 (int_arm_neon_vqrdmlah (v4i32 QPR:$src1), (v4i32 QPR:$Vn),
4553 (v4i32 QPR:$Vm))),
4554 (v4i32 (VQRDMLAHv4i32 QPR:$src1, QPR:$Vn, QPR:$Vm))>;
4581 def : Pat<(v4i32 (int_arm_neon_vqrdmlah (v4i32 QPR:$src1),
4582 (v4i32 QPR:$src2),
4583 (v4i32 (ARMvduplane (v4i32 QPR:$src3),
4585 (v4i32 (VQRDMLAHslv4i32 (v4i32 QPR:$src1),
4586 (v4i32 QPR:$src2),
4606 def : Pat<(v4i32 (int_arm_neon_vqrdmlsh (v4i32 QPR:$src1), (v4i32 QPR:$Vn),
4607 (v4i32 QPR:$Vm))),
4608 (v4i32 (VQRDMLSHv4i32 QPR:$src1, QPR:$Vn, QPR:$Vm))>;
4634 def : Pat<(v4i32 (int_arm_neon_vqrdmlsh (v4i32 QPR:$src1),
4635 (v4i32 QPR:$src2),
4636 (v4i32 (ARMvduplane (v4i32 QPR:$src3),
4638 (v4i32 (VQRDMLSHslv4i32 (v4i32 QPR:$src1),
4639 (v4i32 QPR:$src2),
4651 def : Pat<(v4i32 (saddsat (v4i32 QPR:$src1),
4652 (v4i32 (int_arm_neon_vqdmull (v4i16 DPR:$Vn),
4659 def : Pat<(v4i32 (saddsat (v4i32 QPR:$src1),
4660 (v4i32 (int_arm_neon_vqdmull (v4i16 DPR:$Vn),
4710 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
4711 (mul (v4i32 QPR:$src2),
4712 (v4i32 (ARMvduplane (v4i32 QPR:$src3), imm:$lane))))),
4713 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
4743 def : Pat<(v4i32 (ssubsat (v4i32 QPR:$src1),
4744 (v4i32 (int_arm_neon_vqdmull (v4i16 DPR:$Vn),
4751 def : Pat<(v4i32 (ssubsat (v4i32 QPR:$src1),
4752 (v4i32 (int_arm_neon_vqdmull (v4i16 DPR:$Vn),
4834 def VUDOTQ : VDOT<1, 1, 0, QPR, "vudot", "u8", v4i32, v16i8, int_arm_neon_udot>;
4835 def VSDOTQ : VDOT<1, 0, 0, QPR, "vsdot", "s8", v4i32, v16i8, int_arm_neon_sdot>;
4865 defm VUDOTQI : DOTI<"vudot", "u8", 0b1, 0b1, QPR, v4i32, v16i8,
4867 defm VSDOTQI : DOTI<"vsdot", "s8", 0b1, 0b0, QPR, v4i32, v16i8,
4877 [(set (v4i32 QPR:$dst), (OpNode (v4i32 QPR:$Vd),
4923 def VUSDOTQ : VDOT<1, 0, 1, QPR, "vusdot", "s8", v4i32, v16i8, int_arm_neon_usdot>;
4927 defm VUSDOTQI : N3VMixedDotLane<1, 0, "vusdot", "s8", QPR, v4i32, v16i8,
4930 defm VSUDOTQI : SUDOTLane<1, QPR, v4i32, v16i8, (EXTRACT_SUBREG QPR:$Vm, dsub_0)>;
5124 def : Pat<(v4i16 (trunc (ARMvshruImm (sub (v4i32 QPR:$Vn), QPR:$Vm), 16))),
5137 def VCEQfq : N3VQ_cmp<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
5157 def VCGEfq : N3VQ_cmp<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
5180 def VCGTfq : N3VQ_cmp<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
5200 "f32", v4i32, v4f32, int_arm_neon_vacge, 0>;
5211 "f32", v4i32, v4f32, int_arm_neon_vacgt, 0>;
5320 v4i32, v4i32, and, 1>;
5326 v4i32, v4i32, xor, 1>;
5332 v4i32, v4i32, or, 1>;
5389 (v4i32 (ARMvorrImm QPR:$src, timm:$SIMM)))]> {
5404 [(set QPR:$Vd, (v4i32 (and QPR:$Vn,
5445 (v4i32 (ARMvbicImm QPR:$src, timm:$SIMM)))]> {
5458 [(set QPR:$Vd, (v4i32 (or QPR:$Vn,
5494 [(set QPR:$Vd, (v4i32 (ARMvmvnImm timm:$SIMM)))]> {
5507 [(set QPR:$Vd, (v4i32 (vnotq QPR:$Vm)))]>;
5567 (v4i32 (NEONvbsp QPR:$src1, QPR:$Vn, QPR:$Vm)))]>;
5575 def : Pat<(v4i32 (int_arm_neon_vbsl (v4i32 QPR:$src1),
5576 (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))),
5591 def : Pat<(v4i32 (or (and QPR:$Vn, QPR:$Vd),
5667 def : Pat<(v4i32 (zext (abdu (v4i16 DPR:$opA), (v4i16 DPR:$opB)))),
5849 v4i32, v4i32, int_arm_neon_vrecpe>;
5887 v4i32, v4i32, int_arm_neon_vrsqrte>;
5942 def : Pat<(v4i32 (ARMvshls (v4i32 QPR:$Dn), (v4i32 QPR:$Dm))),
5959 def : Pat<(v4i32 (ARMvshlu (v4i32 QPR:$Dn), (v4i32 QPR:$Dm))),
5993 v4i32, v4i16, imm16>;
6000 def : Pat<(v4i32 (ARMvshlImm (zext (v4i16 DPR:$Rn)), (i32 16))),
6006 def : Pat<(v4i32 (ARMvshlImm (sext (v4i16 DPR:$Rn)), (i32 16))),
6012 def : Pat<(v4i32 (ARMvshlImm (anyext (v4i16 DPR:$Rn)), (i32 16))),
6026 def : Pat<(v4i16 (trunc (ARMvshruImm (v4i32 QPR:$Vn), shr_imm16:$amt))),
6151 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
6179 def : Pat<(v4i32 (vnegq QPR:$src)), (VNEGs32q QPR:$src)>;
6262 [(set QPR:$Vd, (v4i32 (ARMvmovImm timm:$SIMM)))]> {
6352 [(set QPR:$Vd, (v4i32 ARMimmAllZerosV))],
6434 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
6443 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
6578 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
6579 (v4i32 (INSERT_SUBREG QPR:$src1,
6624 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
6625 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
6650 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
6701 def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32, VectorIndex32> {
6728 def : Pat<(v4i32 (ARMvduplane (v4i32 QPR:$src), imm:$lane)),
6729 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
6784 def : Pat<(v4i32 (anyext (v4i16 DPR:$Vm))), (VMOVLuv4i32 DPR:$Vm)>;
6801 v4i32, v4f32, fp_to_sint>;
6803 v4i32, v4f32, fp_to_uint>;
6805 v4f32, v4i32, sint_to_fp>;
6807 v4f32, v4i32, uint_to_fp>;
6842 "s32.f32", v4i32, v4f32, IntS>, Requires<[HasV8, HasNEON]>;
6846 "u32.f32", v4i32, v4f32, IntU>, Requires<[HasV8, HasNEON]>;
6891 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
6893 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
6895 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
6897 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
6984 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
7056 def : AlignedVEXTq<v2i32, v4i32, DSubReg_i32_reg>;
7126 def VEXTq32 : VEXTq<"vext", "32", v4i32, imm0_3> {
7340 !strconcat("sha", op), "32", v4i32, v4i32, Int>;
7344 !strconcat("sha", op), "32", v4i32, v4i32, Int>;
7347 !strconcat("sha", op), "32", v4i32, v4i32, Int>;
7380 def : Pat<(v4i32 (int_arm_neon_sha1c v4i32:$hash_abcd, i32:$hash_e, v4i32:$wk)),
7381 (SHA1C v4i32:$hash_abcd,
7385 v4i32:$wk)>;
7387 def : Pat<(v4i32 (int_arm_neon_sha1m v4i32:$hash_abcd, i32:$hash_e, v4i32:$wk)),
7388 (SHA1M v4i32:$hash_abcd,
7392 v4i32:$wk)>;
7394 def : Pat<(v4i32 (int_arm_neon_sha1p v4i32:$hash_abcd, i32:$hash_e, v4i32:$wk)),
7395 (SHA1P v4i32:$hash_abcd,
7399 v4i32:$wk)>;
7491 def : VFPPat<(f64 (sint_to_fp (extractelt (v4i32 QPR:$src), imm:$lane))),
7495 def : VFPPat<(f64 (uint_to_fp (extractelt (v4i32 QPR:$src), imm:$lane))),
7530 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
7531 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
7598 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
7605 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
7618 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
7619 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
7620 def : Pat<(v4i32 (bitconvert (v8f16 QPR:$src))), (v4i32 QPR:$src)>;
7621 def : Pat<(v4i32 (bitconvert (v8bf16 QPR:$src))), (v4i32 QPR:$src)>;
7622 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
7623 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
7628 def : Pat<(v8f16 (bitconvert (v4i32 QPR:$src))), (v8f16 QPR:$src)>;
7634 def : Pat<(v8bf16 (bitconvert (v4i32 QPR:$src))), (v8bf16 QPR:$src)>;
7640 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
7646 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
7710 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (VREV64q32 QPR:$src)>;
7717 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (VREV64q32 QPR:$src)>;
7730 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (VREV64q32 QPR:$src)>;
7731 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (VREV64q32 QPR:$src)>;
7732 def : Pat<(v4i32 (bitconvert (v8f16 QPR:$src))), (VREV32q16 QPR:$src)>;
7733 def : Pat<(v4i32 (bitconvert (v8bf16 QPR:$src))), (VREV32q16 QPR:$src)>;
7734 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (VREV32q16 QPR:$src)>;
7735 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (VREV32q8 QPR:$src)>;
7740 def : Pat<(v8f16 (bitconvert (v4i32 QPR:$src))), (VREV32q16 QPR:$src)>;
7746 def : Pat<(v8bf16 (bitconvert (v4i32 QPR:$src))), (VREV32q16 QPR:$src)>;
7752 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (VREV32q16 QPR:$src)>;
7758 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (VREV32q8 QPR:$src)>;
7771 foreach VT = [ v16i8, v8i16, v8f16, v8bf16, v4i32, v4f32, v2i64, v2f64 ] in
7772 foreach VT2 = [ v16i8, v8i16, v8f16, v8bf16, v4i32, v4f32, v2i64, v2f64 ] in
7888 // Pat<(v4i32 (extloadvi8 addrmode6oneL32:$addr))
8028 defm : Lengthen_Single<"4", "i32", "16">; // v4i16 -> v4i32
8035 // Double lengthening - v4i8 -> v4i16 -> v4i32
8047 // Double lengthening - v4i8 -> v4i16 -> v4i32
8094 def : Pat<(v4i32 (concat_vectors DPR:$Dn, DPR:$Dm)),