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Searched refs:subregs (Results 1 – 25 of 47) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfoDMR.td44 class DMRROWp<bits<5> num, string n, list<Register> subregs> : PPCReg<n> {
46 let SubRegs = subregs;
49 // WACC - Wide ACC registers. Accumulator registers that are subregs of DMR.
50 // These ACC registers no longer include VSR regs as subregs.
51 class WACC<bits<3> num, string n, list<Register> subregs> : PPCReg<n> {
53 let SubRegs = subregs;
59 class WACC_HI<bits<3> num, string n, list<Register> subregs> : PPCReg<n> {
61 let SubRegs = subregs;
64 class DMR<bits<3> num, string n, list<Register> subregs> : PPCReg<n> {
66 let SubRegs = subregs;
[all …]
H A DPPCRegisterInfoMMA.td20 class ACC<bits<3> num, string n, list<Register> subregs> : PPCReg<n> {
22 let SubRegs = subregs;
29 class UACC<bits<3> num, string n, list<Register> subregs> : PPCReg<n> {
31 let SubRegs = subregs;
H A DPPCRegisterInfo.td48 class SPE<string n, bits<5> Enc, list<Register> subregs = []> : PPCReg<n> {
50 let SubRegs = subregs;
103 class CR<bits<3> num, string n, list<Register> subregs> : PPCReg<n> {
105 let SubRegs = subregs;
114 class VSRPair<bits<5> num, string n, list<Register> subregs> : PPCReg<n> {
116 let SubRegs = subregs;
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVERegisterInfo.td13 class VEReg<bits<7> enc, string n, list<Register> subregs = [],
19 let SubRegs = subregs;
29 class VEVecReg<bits<8> enc, string n, list<Register> subregs = [],
35 let SubRegs = subregs;
39 class VEMaskReg<bits<4> enc, string n, list<Register> subregs = [],
45 let SubRegs = subregs;
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.td34 class MipsRegWithSubRegs<bits<16> Enc, string n, list<Register> subregs>
35 : RegisterWithSubRegs<n, subregs> {
44 class Mips64GPRReg<bits<16> Enc, string n, list<Register> subregs>
45 : MipsRegWithSubRegs<Enc, n, subregs> {
53 class AFPR<bits<16> Enc, string n, list<Register> subregs>
54 : MipsRegWithSubRegs<Enc, n, subregs> {
59 class AFPR64<bits<16> Enc, string n, list<Register> subregs>
60 : MipsRegWithSubRegs<Enc, n, subregs> {
66 class AFPR128<bits<16> Enc, string n, list<Register> subregs>
67 : MipsRegWithSubRegs<Enc, n, subregs> {
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DLiveVariables.cpp224 for (MCPhysReg SubReg : TRI->subregs(Reg)) { in FindLastPartialDef()
275 for (MCPhysReg SubReg : TRI->subregs(Reg)) { in HandlePhysRegUse()
286 for (MCPhysReg SS : TRI->subregs(SubReg)) in HandlePhysRegUse()
312 for (MCPhysReg SubReg : TRI->subregs(Reg)) { in FindLastRefOrPartRef()
360 for (MCPhysReg SubReg : TRI->subregs(Reg)) { in HandlePhysRegKill()
389 for (MCPhysReg SubReg : TRI->subregs(Reg)) { in HandlePhysRegKill()
412 for (MCPhysReg SS : TRI->subregs(SubReg)) in HandlePhysRegKill()
470 for (MCPhysReg SubReg : TRI->subregs(Reg)) { in HandlePhysRegDef()
490 for (MCPhysReg SubReg : TRI->subregs(Reg)) { in HandlePhysRegDef()
H A DRegUsageInfoCollector.cpp214 for (MCPhysReg SR : TRI.subregs(Reg)) in computeCalleeSavedRegs()
H A DMachineInstrBundle.cpp199 for (MCPhysReg SubReg : TRI->subregs(Reg)) { in finalizeBundle()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.td27 class HexagonDoubleReg<bits<5> num, string n, list<Register> subregs,
29 RegisterWithSubRegs<n, subregs> {
40 class HexagonDoubleSys<bits<7> num, string n, list<Register> subregs,
42 RegisterWithSubRegs<n, subregs> {
63 class Rd<bits<5> num, string n, list<Register> subregs,
65 HexagonDoubleReg<num, n, subregs, alt> {
66 let SubRegs = subregs;
84 class Rcc<bits<5> num, string n, list<Register> subregs,
86 HexagonDoubleReg<num, n, subregs, alt> {
87 let SubRegs = subregs;
[all …]
H A DHexagonBlockRanges.cpp272 if (TRI.subregs(R.Reg).empty()) in expandToSubRegs()
274 for (MCPhysReg I : TRI.subregs(R.Reg)) in expandToSubRegs()
357 if (!TRI.subregs(PR).empty()) in computeInitialLiveRanges()
376 assert(!S.Reg.isPhysical() || TRI.subregs(S.Reg).empty()); in computeInitialLiveRanges()
384 assert(!S.Reg.isPhysical() || TRI.subregs(S.Reg).empty()); in computeInitialLiveRanges()
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFRegisterInfo.td24 class Ri<bits<16> Enc, string n, list<Register> subregs>
25 : RegisterWithSubRegs<n, subregs> {
/freebsd/contrib/llvm-project/llvm/lib/MCA/HardwareUnits/
H A DRegisterFile.cpp130 for (MCPhysReg I : MRI.subregs(RegID)) { in onInstructionExecuted()
185 for (MCPhysReg I : MRI.subregs(Reg)) { in addRegisterFile()
285 for (MCPhysReg I : MRI.subregs(ZeroRegisterID)) in addRegisterWrite()
307 for (MCPhysReg I : MRI.subregs(RegID)) { in addRegisterWrite()
368 for (MCPhysReg I : MRI.subregs(RegID)) { in removeRegisterWrite()
475 for (MCPhysReg I : MRI.subregs(AliasReg)) in tryEliminateMoveOrSwap()
533 for (MCPhysReg I : MRI.subregs(RegID)) { in collectWrites()
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaRegisterInfo.td19 class XtensaRegWithSubRegs<string n, list<Register> subregs>
20 : RegisterWithSubRegs<n, subregs> {
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiRegisterInfo.td12 class LanaiReg<bits<5> num, string n, list<Register> subregs = [],
17 let SubRegs = subregs;
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600RegisterInfo.td19 class R600Reg_128<string n, list<Register> subregs, bits<16> encoding> :
20 RegisterWithSubRegs<n, subregs> {
28 class R600Reg_64<string n, list<Register> subregs, bits<16> encoding> :
29 RegisterWithSubRegs<n, subregs> {
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430RegisterInfo.td21 class MSP430RegWithSubregs<bits<4> num, string n, list<Register> subregs,
23 : RegisterWithSubRegs<n, subregs> {
/freebsd/contrib/llvm-project/llvm/lib/MC/
H A DMCRegisterInfo.cpp122 for (MCPhysReg Sub : subregs(Reg)) { in getSubReg()
136 for (MCPhysReg Sub : subregs(Reg)) { in getSubRegIndex()
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.td41 class Rdi<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> {
42 let SubRegs = subregs;
50 class Rd<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> {
51 let SubRegs = subregs;
57 class Rq<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> {
58 let SubRegs = subregs;
/freebsd/contrib/llvm-project/lldb/source/Plugins/ABI/X86/
H A DABIX86.cpp71 llvm::ArrayRef<RegData *> subregs, uint32_t base_size, in addPartialRegisters() argument
74 for (const RegData *subreg : subregs) { in addPartialRegisters()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCChecker.cpp82 for (MCRegAliasIterator SRI(R, &RI, RI.subregs(R).empty()); SRI.isValid(); in initReg()
84 if (RI.subregs(*SRI).empty()) in initReg()
148 for (MCRegAliasIterator SRI(R, &RI, RI.subregs(R).empty()); SRI.isValid(); in init()
150 if (!RI.subregs(*SRI).empty()) in init()
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.td14 class AVRReg<bits<16> num, string name, list<Register> subregs = [],
15 list<string> altNames = []> : RegisterWithSubRegs<name, subregs> {
20 let SubRegs = subregs;
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchRegisterInfo.td20 class LoongArchRegWithSubRegs<bits<16> Enc, string n, list<Register> subregs,
22 : RegisterWithSubRegs<n, subregs> {
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.td17 class SystemZRegWithSubregs<string n, list<Register> subregs>
18 : RegisterWithSubRegs<n, subregs> {
142 // Not used directly, but needs to exist for ADDR32 and ADDR64 subregs
/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCRegisterInfo.h238 iterator_range<MCSubRegIterator> subregs(MCRegister Reg) const;
761 MCRegisterInfo::subregs(MCRegister Reg) const { in subregs() function
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMRegisterInfo.td16 class ARMReg<bits<16> Enc, string n, list<Register> subregs = [],
20 let SubRegs = subregs;
476 // 32-bit SPR subregs).
500 // Subset of QPR that have 32-bit SPR subregs.
506 // Subset of QPR that have DPR_8 and SPR_8 subregs.

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