1*bdd1243dSDimitry Andric//===- XtensaRegisterInfo.td - Xtensa Register defs --------*- tablegen -*-===// 2*bdd1243dSDimitry Andric// 3*bdd1243dSDimitry Andric// The LLVM Compiler Infrastructure 4*bdd1243dSDimitry Andric// 5*bdd1243dSDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 6*bdd1243dSDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 7*bdd1243dSDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 8*bdd1243dSDimitry Andric// 9*bdd1243dSDimitry Andric//===----------------------------------------------------------------------===// 10*bdd1243dSDimitry Andric 11*bdd1243dSDimitry Andric//===----------------------------------------------------------------------===// 12*bdd1243dSDimitry Andric// Class definitions. 13*bdd1243dSDimitry Andric//===----------------------------------------------------------------------===// 14*bdd1243dSDimitry Andric 15*bdd1243dSDimitry Andricclass XtensaReg<string n> : Register<n> { 16*bdd1243dSDimitry Andric let Namespace = "Xtensa"; 17*bdd1243dSDimitry Andric} 18*bdd1243dSDimitry Andric 19*bdd1243dSDimitry Andricclass XtensaRegWithSubRegs<string n, list<Register> subregs> 20*bdd1243dSDimitry Andric : RegisterWithSubRegs<n, subregs> { 21*bdd1243dSDimitry Andric let Namespace = "Xtensa"; 22*bdd1243dSDimitry Andric} 23*bdd1243dSDimitry Andric 24*bdd1243dSDimitry Andric//===----------------------------------------------------------------------===// 25*bdd1243dSDimitry Andric// General-purpose registers 26*bdd1243dSDimitry Andric//===----------------------------------------------------------------------===// 27*bdd1243dSDimitry Andric 28*bdd1243dSDimitry Andric// Xtensa general purpose regs 29*bdd1243dSDimitry Andricclass ARReg<bits<4> num, string n, list<string> alt = []> : XtensaReg<n> { 30*bdd1243dSDimitry Andric let HWEncoding{3-0} = num; 31*bdd1243dSDimitry Andric let AltNames = alt; 32*bdd1243dSDimitry Andric} 33*bdd1243dSDimitry Andric 34*bdd1243dSDimitry Andric// Return Address 35*bdd1243dSDimitry Andricdef A0 : ARReg<0, "a0">, DwarfRegNum<[0]>; 36*bdd1243dSDimitry Andric 37*bdd1243dSDimitry Andric// Stack Pointer (callee-saved) 38*bdd1243dSDimitry Andricdef SP : ARReg<1, "a1", ["sp"]>, DwarfRegNum<[1]>; 39*bdd1243dSDimitry Andric 40*bdd1243dSDimitry Andric// Function Arguments 41*bdd1243dSDimitry Andricdef A2 : ARReg<2, "a2">, DwarfRegNum<[2]>; 42*bdd1243dSDimitry Andricdef A3 : ARReg<3, "a3">, DwarfRegNum<[3]>; 43*bdd1243dSDimitry Andricdef A4 : ARReg<4, "a4">, DwarfRegNum<[4]>; 44*bdd1243dSDimitry Andricdef A5 : ARReg<5, "a5">, DwarfRegNum<[5]>; 45*bdd1243dSDimitry Andricdef A6 : ARReg<6, "a6">, DwarfRegNum<[6]>; 46*bdd1243dSDimitry Andricdef A7 : ARReg<7, "a7">, DwarfRegNum<[7]>; 47*bdd1243dSDimitry Andric 48*bdd1243dSDimitry Andric// Static Chain 49*bdd1243dSDimitry Andricdef A8 : ARReg<8, "a8">, DwarfRegNum<[8]>; 50*bdd1243dSDimitry Andric 51*bdd1243dSDimitry Andricdef A9 : ARReg<9, "a9">, DwarfRegNum<[9]>; 52*bdd1243dSDimitry Andricdef A10 : ARReg<10, "a10">, DwarfRegNum<[10]>; 53*bdd1243dSDimitry Andricdef A11 : ARReg<11, "a11">, DwarfRegNum<[11]>; 54*bdd1243dSDimitry Andric 55*bdd1243dSDimitry Andric// Callee-saved 56*bdd1243dSDimitry Andricdef A12 : ARReg<12, "a12">, DwarfRegNum<[12]>; 57*bdd1243dSDimitry Andricdef A13 : ARReg<13, "a13">, DwarfRegNum<[13]>; 58*bdd1243dSDimitry Andricdef A14 : ARReg<14, "a14">, DwarfRegNum<[14]>; 59*bdd1243dSDimitry Andric 60*bdd1243dSDimitry Andric// Stack-Frame Pointer (optional) - Callee-Saved 61*bdd1243dSDimitry Andricdef A15 : ARReg<15, "a15">, DwarfRegNum<[15]>; 62*bdd1243dSDimitry Andric 63*bdd1243dSDimitry Andric// Register class with allocation order 64*bdd1243dSDimitry Andricdef AR : RegisterClass<"Xtensa", [i32], 32, (add 65*bdd1243dSDimitry Andric A8, A9, A10, A11, A12, A13, A14, A15, 66*bdd1243dSDimitry Andric A7, A6, A5, A4, A3, A2, A0, SP)>; 67*bdd1243dSDimitry Andric//===----------------------------------------------------------------------===// 68*bdd1243dSDimitry Andric// Special-purpose registers 69*bdd1243dSDimitry Andric//===----------------------------------------------------------------------===// 70*bdd1243dSDimitry Andricclass SRReg<bits<8> num, string n, list<string> alt = []> : XtensaReg<n> { 71*bdd1243dSDimitry Andric let HWEncoding{7-0} = num; 72*bdd1243dSDimitry Andric let AltNames = alt; 73*bdd1243dSDimitry Andric} 74*bdd1243dSDimitry Andric 75*bdd1243dSDimitry Andric// Shift Amount Register 76*bdd1243dSDimitry Andricdef SAR : SRReg<3, "sar", ["SAR","3"]>; 77*bdd1243dSDimitry Andric 78*bdd1243dSDimitry Andricdef SR : RegisterClass<"Xtensa", [i32], 32, (add SAR)>; 79