1//===-- BPFRegisterInfo.td - BPF Register defs -------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// Declarations that describe the BPF register file 11//===----------------------------------------------------------------------===// 12 13let Namespace = "BPF" in { 14 def sub_32 : SubRegIndex<32>; 15} 16 17class Wi<bits<16> Enc, string n> : Register<n> { 18 let HWEncoding = Enc; 19 let Namespace = "BPF"; 20} 21 22// Registers are identified with 4-bit ID numbers. 23// Ri - 64-bit integer registers 24class Ri<bits<16> Enc, string n, list<Register> subregs> 25 : RegisterWithSubRegs<n, subregs> { 26 let HWEncoding = Enc; 27 let Namespace = "BPF"; 28 let SubRegIndices = [sub_32]; 29} 30 31foreach I = 0-11 in { 32 // 32-bit Integer (alias to low part of 64-bit register). 33 def W#I : Wi<I, "w"#I>, DwarfRegNum<[I]>; 34 // 64-bit Integer registers 35 def R#I : Ri<I, "r"#I, [!cast<Wi>("W"#I)]>, DwarfRegNum<[I]>; 36} 37 38// Register classes. 39def GPR32 : RegisterClass<"BPF", [i32], 64, (add 40 (sequence "W%u", 1, 9), 41 W0, // Return value 42 W11, // Stack Ptr 43 W10 // Frame Ptr 44)>; 45 46def GPR : RegisterClass<"BPF", [i64], 64, (add 47 (sequence "R%u", 1, 9), 48 R0, // Return value 49 R11, // Stack Ptr 50 R10 // Frame Ptr 51)>; 52