1*0b57cec5SDimitry Andric//===- LanaiRegisterInfo.td - Lanai Register defs ------------*- tablegen -*-===// 2*0b57cec5SDimitry Andric// 3*0b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*0b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 5*0b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*0b57cec5SDimitry Andric// 7*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 8*0b57cec5SDimitry Andric// Declarations that describe the Lanai register file 9*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 10*0b57cec5SDimitry Andric 11*0b57cec5SDimitry Andric// Registers are identified with 5-bit ID numbers. 12*0b57cec5SDimitry Andricclass LanaiReg<bits<5> num, string n, list<Register> subregs = [], 13*0b57cec5SDimitry Andric list<string> altNames = []> : Register<n, altNames> { 14*0b57cec5SDimitry Andric field bits<5> Num; 15*0b57cec5SDimitry Andric let Num = num; 16*0b57cec5SDimitry Andric let Namespace = "Lanai"; 17*0b57cec5SDimitry Andric let SubRegs = subregs; 18*0b57cec5SDimitry Andric} 19*0b57cec5SDimitry Andric 20*0b57cec5SDimitry Andriclet Namespace = "Lanai" in { 21*0b57cec5SDimitry Andric def sub_32 : SubRegIndex<32>; 22*0b57cec5SDimitry Andric} 23*0b57cec5SDimitry Andric 24*0b57cec5SDimitry Andric// Integer registers 25*0b57cec5SDimitry Andricforeach i = 0-31 in { 26*0b57cec5SDimitry Andric def R#i : LanaiReg<i, "r"#i>, DwarfRegNum<[i]>; 27*0b57cec5SDimitry Andric} 28*0b57cec5SDimitry Andric 29*0b57cec5SDimitry Andric// Register aliases 30*0b57cec5SDimitry Andriclet SubRegIndices = [sub_32] in { 31*0b57cec5SDimitry Andric def PC : LanaiReg< 2, "pc", [R2]>, DwarfRegAlias<R2>; 32*0b57cec5SDimitry Andric def SP : LanaiReg< 4, "sp", [R4]>, DwarfRegAlias<R4>; 33*0b57cec5SDimitry Andric def FP : LanaiReg< 5, "fp", [R5]>, DwarfRegAlias<R5>; 34*0b57cec5SDimitry Andric def RV : LanaiReg< 8, "rv", [R8]>, DwarfRegAlias<R8>; 35*0b57cec5SDimitry Andric def RR1 : LanaiReg<10, "rr1", [R10]>, DwarfRegAlias<R10>; 36*0b57cec5SDimitry Andric def RR2 : LanaiReg<11, "rr2", [R11]>, DwarfRegAlias<R11>; 37*0b57cec5SDimitry Andric def RCA : LanaiReg<15, "rca", [R15]>, DwarfRegAlias<R15>; 38*0b57cec5SDimitry Andric} 39*0b57cec5SDimitry Andric 40*0b57cec5SDimitry Andric// Define a status register to capture the dependencies between the set flag 41*0b57cec5SDimitry Andric// and setcc instructions 42*0b57cec5SDimitry Andricdef SR : LanaiReg< 0, "sw">; 43*0b57cec5SDimitry Andric 44*0b57cec5SDimitry Andric// Register classes. 45*0b57cec5SDimitry Andricdef GPR : RegisterClass<"Lanai", [i32], 32, 46*0b57cec5SDimitry Andric (add R3, R9, R12, R13, R14, R16, R17, 47*0b57cec5SDimitry Andric (sequence "R%i", 20, 31), 48*0b57cec5SDimitry Andric R6, R7, R18, R19, // registers for passing arguments 49*0b57cec5SDimitry Andric R15, RCA, // register for constant addresses 50*0b57cec5SDimitry Andric R10, RR1, R11, RR2, // programmer controlled registers 51*0b57cec5SDimitry Andric R8, RV, // return value 52*0b57cec5SDimitry Andric R5, FP, // frame pointer 53*0b57cec5SDimitry Andric R4, SP, // stack pointer 54*0b57cec5SDimitry Andric R2, PC, // program counter 55*0b57cec5SDimitry Andric R1, // all 1s (0xffffffff) 56*0b57cec5SDimitry Andric R0 // constant 0 57*0b57cec5SDimitry Andric )>; 58*0b57cec5SDimitry Andric 59*0b57cec5SDimitry Andric// Condition code register class 60*0b57cec5SDimitry Andricdef CCR : RegisterClass<"Lanai", [i32], 32, (add SR)> { 61*0b57cec5SDimitry Andric let CopyCost = -1; // Don't allow copying of status registers 62*0b57cec5SDimitry Andric let isAllocatable = 0; 63*0b57cec5SDimitry Andric} 64