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Searched refs:reg_val (Results 1 – 25 of 70) sorted by relevance

123

/freebsd/sys/dev/liquidio/base/
H A Dcn23xx_pf_device.c142 uint64_t reg_val; in lio_cn23xx_pf_setup_global_mac_regs() local
150 reg_val = in lio_cn23xx_pf_setup_global_mac_regs()
154 reg_val = pf_num * LIO_CN23XX_PF_MAX_RINGS; in lio_cn23xx_pf_setup_global_mac_regs()
157 reg_val = reg_val | in lio_cn23xx_pf_setup_global_mac_regs()
162 reg_val); in lio_cn23xx_pf_setup_global_mac_regs()
197 volatile uint64_t reg_val = in lio_cn23xx_pf_reset_io_queues() local
200 while ((reg_val & LIO_CN23XX_PKT_INPUT_CTL_RST) && in lio_cn23xx_pf_reset_io_queues()
201 !(reg_val & LIO_CN23XX_PKT_INPUT_CTL_QUIET) && in lio_cn23xx_pf_reset_io_queues()
203 reg_val = lio_read_csr64(oct, in lio_cn23xx_pf_reset_io_queues()
215 reg_val &= ~LIO_CN23XX_PKT_INPUT_CTL_RST; in lio_cn23xx_pf_reset_io_queues()
[all …]
/freebsd/sys/arm/allwinner/
H A Dif_emac.c312 uint32_t reg_val, rxcount; in emac_rxeof() local
332 reg_val = EMAC_READ_REG(sc, EMAC_RX_IO_DATA); in emac_rxeof()
333 if (reg_val != EMAC_PACKET_HEADER) { in emac_rxeof()
338 reg_val = EMAC_READ_REG(sc, EMAC_CTL); in emac_rxeof()
339 reg_val &= ~EMAC_CTL_RX_EN; in emac_rxeof()
340 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val); in emac_rxeof()
343 reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL); in emac_rxeof()
344 reg_val |= EMAC_RX_FLUSH_FIFO; in emac_rxeof()
345 EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val); in emac_rxeof()
360 reg_val = EMAC_READ_REG(sc, EMAC_CTL); in emac_rxeof()
[all …]
/freebsd/sys/arm/qualcomm/
H A Dqcom_cpu_kpssv2.c81 uint32_t reg_val; in qcom_cpu_kpssv2_regulator_start() local
138 reg_val = (64 << QCOM_APC_PWR_GATE_CTL_BHS_CNT_SHIFT) in qcom_cpu_kpssv2_regulator_start()
141 bus_space_write_4(acc_tag, acc_handle, QCOM_APC_PWR_GATE_CTL, reg_val); in qcom_cpu_kpssv2_regulator_start()
149 reg_val |= 0x3f << QCOM_APC_PWR_GATE_CTL_BHS_SEG_SHIFT; in qcom_cpu_kpssv2_regulator_start()
150 bus_space_write_4(acc_tag, acc_handle, QCOM_APC_PWR_GATE_CTL, reg_val); in qcom_cpu_kpssv2_regulator_start()
158 reg_val |= 0x3f << QCOM_APC_PWR_GATE_CTL_LDO_BYP_SHIFT; in qcom_cpu_kpssv2_regulator_start()
159 bus_space_write_4(acc_tag, acc_handle, QCOM_APC_PWR_GATE_CTL, reg_val); in qcom_cpu_kpssv2_regulator_start()
172 reg_val = QCOM_APCS_CPU_PWR_CTL_COREPOR_RST in qcom_cpu_kpssv2_regulator_start()
174 bus_space_write_4(acc_tag, acc_handle, QCOM_APCS_CPU_PWR_CTL, reg_val); in qcom_cpu_kpssv2_regulator_start()
181 reg_val &= ~QCOM_APCS_CPU_PWR_CTL_CLAMP; in qcom_cpu_kpssv2_regulator_start()
[all …]
/freebsd/sys/arm/ti/
H A Dti_pinmux.c133 uint16_t reg_val; in ti_pinmux_padconf_set_internal() local
136 reg_val = (uint16_t)(state & ti_pinmux_dev->padconf_sate_mask); in ti_pinmux_padconf_set_internal()
153 reg_val |= (uint16_t)(mode & ti_pinmux_dev->padconf_muxmode_mask); in ti_pinmux_padconf_set_internal()
157 reg_val, muxmode); in ti_pinmux_padconf_set_internal()
159 ti_pinmux_write_2(sc, padconf->reg_off, reg_val); in ti_pinmux_padconf_set_internal()
213 uint16_t reg_val; in ti_pinmux_padconf_get() local
224 reg_val = ti_pinmux_read_2(ti_pinmux_sc, padconf->reg_off); in ti_pinmux_padconf_get()
228 *state = (reg_val & ti_pinmux_dev->padconf_sate_mask); in ti_pinmux_padconf_get()
232 *muxmode = padconf->muxmodes[(reg_val & ti_pinmux_dev->padconf_muxmode_mask)]; in ti_pinmux_padconf_get()
255 uint16_t reg_val; in ti_pinmux_padconf_set_gpiomode() local
[all …]
/freebsd/sys/contrib/dev/athk/ath10k/
H A Dhw.c747 u32 addr, reg_val, mem_val; in ath10k_hw_qca6174_enable_pll_clock() local
764 ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val); in ath10k_hw_qca6174_enable_pll_clock()
769 if (MS(reg_val, EFUSE_XTAL_SEL) > ATH10K_HW_REFCLK_COUNT) in ath10k_hw_qca6174_enable_pll_clock()
772 hw_clk = &hw->hw_clk[MS(reg_val, EFUSE_XTAL_SEL)]; in ath10k_hw_qca6174_enable_pll_clock()
776 ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val); in ath10k_hw_qca6174_enable_pll_clock()
780 reg_val &= ~(BB_PLL_CONFIG_FRAC_MASK | BB_PLL_CONFIG_OUTDIV_MASK); in ath10k_hw_qca6174_enable_pll_clock()
781 reg_val |= (SM(hw_clk->rnfrac, BB_PLL_CONFIG_FRAC) | in ath10k_hw_qca6174_enable_pll_clock()
783 ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val); in ath10k_hw_qca6174_enable_pll_clock()
789 ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val); in ath10k_hw_qca6174_enable_pll_clock()
793 reg_val &= ~WLAN_PLL_SETTLE_TIME_MASK; in ath10k_hw_qca6174_enable_pll_clock()
[all …]
H A Dbmi.c199 int ath10k_bmi_write_soc_reg(struct ath10k *ar, u32 address, u32 reg_val) in ath10k_bmi_write_soc_reg() argument
207 address, reg_val); in ath10k_bmi_write_soc_reg()
216 cmd.write_soc_reg.value = __cpu_to_le32(reg_val); in ath10k_bmi_write_soc_reg()
228 int ath10k_bmi_read_soc_reg(struct ath10k *ar, u32 address, u32 *reg_val) in ath10k_bmi_read_soc_reg() argument
254 *reg_val = __le32_to_cpu(resp.read_soc_reg.value); in ath10k_bmi_read_soc_reg()
257 *reg_val); in ath10k_bmi_read_soc_reg()
/freebsd/sys/dev/qat/qat_hw/qat_c4xxx/
H A Dadf_c4xxx_ras.c919 u32 reg_val = 0; in adf_handle_parser_uerr() local
921 reg_val = ADF_CSR_RD(aram_base_addr, ADF_C4XXX_IC_PARSER_UERR + offset); in adf_handle_parser_uerr()
922 if (reg_val & ADF_C4XXX_PARSER_UERR_INTR) { in adf_handle_parser_uerr()
924 reg_val &= ~ADF_C4XXX_PARSER_DESC_UERR_INTR_ENA; in adf_handle_parser_uerr()
927 reg_val); in adf_handle_parser_uerr()
946 u64 reg_val; in adf_handle_mac_intr() local
948 reg_val = ADF_CSR_RD64(aram_base_addr, ADF_C4XXX_MAC_IP + offset); in adf_handle_mac_intr()
951 if (reg_val & ADF_C4XXX_MAC_ERROR_TX_UNDERRUN) in adf_handle_mac_intr()
957 if (reg_val & ADF_C4XXX_MAC_ERROR_TX_FCS) in adf_handle_mac_intr()
960 if (reg_val & ADF_C4XXX_MAC_ERROR_TX_DATA_CORRUPT) in adf_handle_mac_intr()
[all …]
/freebsd/sys/dev/qlnx/qlnxe/
H A Decore_init_fw_funcs.c658 u32 reg_val, i; in ecore_poll_on_qm_cmd_ready() local
660 for (i = 0, reg_val = 0; i < QM_STOP_CMD_MAX_POLL_COUNT && !reg_val; i++) { in ecore_poll_on_qm_cmd_ready()
662 reg_val = ecore_rd(p_hwfn, p_ptt, QM_REG_SDMCMDREADY); in ecore_poll_on_qm_cmd_ready()
1290 u32 reg_val; in ecore_set_vxlan_enable() local
1293 reg_val = ecore_rd(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN); in ecore_set_vxlan_enable()
1294 …SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT, vxlan_enable… in ecore_set_vxlan_enable()
1295 ecore_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val); in ecore_set_vxlan_enable()
1296 if (reg_val) /* TODO: handle E5 init */ in ecore_set_vxlan_enable()
1298 reg_val = ecore_rd(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2); in ecore_set_vxlan_enable()
1301 if (reg_val == (u32)PRS_ETH_OUTPUT_FORMAT) in ecore_set_vxlan_enable()
[all …]
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_gpio.c429 u_int32_t reg_val; in ar9300_gpio_set_intr() local
463 reg_val = OS_REG_READ(ah, regs[i]); in ar9300_gpio_set_intr()
465 reg_val &= ~(1 << reg_bit); in ar9300_gpio_set_intr()
466 OS_REG_WRITE(ah, regs[i], reg_val); in ar9300_gpio_set_intr()
470 field_val = (reg_val >> shifts[i]) & gpio_mask; in ar9300_gpio_set_intr()
477 reg_val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL)); in ar9300_gpio_set_intr()
481 reg_val &= ~(1 << reg_bit); in ar9300_gpio_set_intr()
484 reg_val |= (1 << reg_bit); in ar9300_gpio_set_intr()
486 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL), reg_val); in ar9300_gpio_set_intr()
490 reg_val = OS_REG_READ(ah, regs[i]); in ar9300_gpio_set_intr()
[all …]
H A Dar9300_reset.c3255 u_int32_t reg_val;
3270 reg_val = OS_REG_READ(ah, AR9285_AN_RXTXBB1);
3271 reg_val |= ((0x1 << 5) | (0x1 << 7));
3272 OS_REG_WRITE(ah, AR9285_AN_RXTXBB1, reg_val);
3275 reg_val = OS_REG_READ(ah, AR9285_AN_RF2G7);
3276 reg_val &= 0xfffffffd;
3277 OS_REG_WRITE(ah, AR9285_AN_RF2G7, reg_val);
3280 reg_val = OS_REG_READ(ah, AR9285_AN_RF2G1);
3281 reg_val &= 0xfffff7ff;
3282 OS_REG_WRITE(ah, AR9285_AN_RF2G1, reg_val);
[all …]
H A Dar9300_recv.c283 u_int32_t reg_val = 0; in ar9300_promisc_mode() local
284 reg_val = OS_REG_READ(ah, AR_RX_FILTER); in ar9300_promisc_mode()
286 reg_val |= AR_RX_PROM; in ar9300_promisc_mode()
288 reg_val &= ~AR_RX_PROM; in ar9300_promisc_mode()
290 OS_REG_WRITE(ah, AR_RX_FILTER, reg_val); in ar9300_promisc_mode()
/freebsd/sys/dev/ixgbe/
H A Dixgbe_x550.c2088 u32 reg_val; in ixgbe_setup_kr_speed_x550em() local
2092 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val); in ixgbe_setup_kr_speed_x550em()
2096 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; in ixgbe_setup_kr_speed_x550em()
2097 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR | in ixgbe_setup_kr_speed_x550em()
2102 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR; in ixgbe_setup_kr_speed_x550em()
2106 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX; in ixgbe_setup_kr_speed_x550em()
2110 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); in ixgbe_setup_kr_speed_x550em()
2116 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val); in ixgbe_setup_kr_speed_x550em()
2121 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; in ixgbe_setup_kr_speed_x550em()
2122 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN; in ixgbe_setup_kr_speed_x550em()
[all …]
H A Dixgbe_82599.h63 s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, u32 *reg_val);
64 s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 reg_val, bool locked);
/freebsd/sys/dev/axgbe/
H A Dxgbe-common.h1517 uint32_t reg_val = XGMAC_IOREAD((_pdata), _reg); \
1518 SET_BITS(reg_val, \
1521 XGMAC_IOWRITE((_pdata), _reg, reg_val); \
1543 uint32_t reg_val = XGMAC_MTL_IOREAD((_pdata), (_n), _reg); \
1544 SET_BITS(reg_val, \
1547 XGMAC_MTL_IOWRITE((_pdata), (_n), _reg, reg_val); \
1568 uint32_t reg_val = XGMAC_DMA_IOREAD((_channel), _reg); \
1569 SET_BITS(reg_val, \
1572 XGMAC_DMA_IOWRITE((_channel), _reg, reg_val); \
1626 uint16_t reg_val
[all...]
H A Dxgbe-dev.c491 unsigned int reg, reg_val; in xgbe_disable_tx_flow_control() local
503 reg_val = XGMAC_IOREAD(pdata, reg); in xgbe_disable_tx_flow_control()
504 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 0); in xgbe_disable_tx_flow_control()
505 XGMAC_IOWRITE(pdata, reg, reg_val); in xgbe_disable_tx_flow_control()
517 unsigned int reg, reg_val; in xgbe_enable_tx_flow_control() local
541 reg_val = XGMAC_IOREAD(pdata, reg); in xgbe_enable_tx_flow_control()
544 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 1); in xgbe_enable_tx_flow_control()
547 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, 0xffff); in xgbe_enable_tx_flow_control()
549 XGMAC_IOWRITE(pdata, reg, reg_val); in xgbe_enable_tx_flow_control()
1237 unsigned int reg_val = XGMAC_IOREAD(pdata, MAC_MDIOCL22R); in xgbe_set_ext_mii_mode() local
[all …]
/freebsd/sys/dev/qat/qat_common/
H A Dadf_aer.c51 unsigned int aer_offset, reg_val = 0;
57 reg_val = in adf_aer_store_ppaerucm_reg()
60 hw_data->aerucm_mask = reg_val; in adf_aer_store_ppaerucm_reg()
124 u32 aer_offset, reg_val = 0; in adf_dev_pre_reset()
127 reg_val = in adf_dev_pre_reset()
129 reg_val |= ADF_PPAERUCM_MASK; in adf_dev_pre_reset()
132 reg_val, in adf_dev_pre_reset()
55 unsigned int aer_offset, reg_val = 0; adf_aer_store_ppaerucm_reg() local
128 u32 aer_offset, reg_val = 0; adf_dev_pre_reset() local
/freebsd/sys/dev/bxe/
H A Decore_init.h747 uint32_t reg_val; in ecore_set_mcp_parity() local
750 reg_val = REG_RD(sc, mcp_attn_ctl_regs[i].addr); in ecore_set_mcp_parity()
753 reg_val |= MISC_AEU_ENABLE_MCP_PRTY_BITS; /* Linux is using mcp_attn_ctl_regs[i].bits */ in ecore_set_mcp_parity()
755 reg_val &= ~MISC_AEU_ENABLE_MCP_PRTY_BITS; /* Linux is using mcp_attn_ctl_regs[i].bits */ in ecore_set_mcp_parity()
757 REG_WR(sc, mcp_attn_ctl_regs[i].addr, reg_val); in ecore_set_mcp_parity()
799 uint32_t reg_val, mcp_aeu_bits = in ecore_clear_blocks_parity() local
815 reg_val = REG_RD(sc, ecore_blocks_parity_data[i]. in ecore_clear_blocks_parity()
817 if (reg_val & reg_mask) in ecore_clear_blocks_parity()
821 reg_val & reg_mask); in ecore_clear_blocks_parity()
826 reg_val = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_MCP); in ecore_clear_blocks_parity()
[all …]
/freebsd/sys/dev/vnic/
H A Dnicvf_queues.c126 uint64_t reg_val; in nicvf_poll_reg() local
133 reg_val = nicvf_queue_reg_read(nic, reg, qidx); in nicvf_poll_reg()
134 if (((reg_val & bit_mask) >> bit_pos) == val) in nicvf_poll_reg()
2049 uint64_t reg_val; in nicvf_enable_intr() local
2051 reg_val = nicvf_reg_read(nic, NIC_VF_ENA_W1S); in nicvf_enable_intr()
2055 reg_val |= ((1UL << q_idx) << NICVF_INTR_CQ_SHIFT); in nicvf_enable_intr()
2058 reg_val |= ((1UL << q_idx) << NICVF_INTR_SQ_SHIFT); in nicvf_enable_intr()
2061 reg_val |= ((1UL << q_idx) << NICVF_INTR_RBDR_SHIFT); in nicvf_enable_intr()
2064 reg_val |= (1UL << NICVF_INTR_PKT_DROP_SHIFT); in nicvf_enable_intr()
2067 reg_val |= (1UL << NICVF_INTR_TCP_TIMER_SHIFT); in nicvf_enable_intr()
[all …]
/freebsd/sys/dev/mge/
H A Dif_mge.c456 uint32_t reg_idx, reg_off, reg_val, i; in mge_set_ucast_address() local
461 reg_val = (1 | (queue << 1)) << reg_off; in mge_set_ucast_address()
465 MGE_WRITE(sc, MGE_DA_FILTER_UCAST(i), reg_val); in mge_set_ucast_address()
475 uint32_t reg_val, i; in mge_set_prom_mode() local
483 reg_val = ((1 | (queue << 1)) | (1 | (queue << 1)) << 8 | in mge_set_prom_mode()
487 MGE_WRITE(sc, MGE_DA_FILTER_SPEC_MCAST(i), reg_val); in mge_set_prom_mode()
488 MGE_WRITE(sc, MGE_DA_FILTER_OTH_MCAST(i), reg_val); in mge_set_prom_mode()
492 MGE_WRITE(sc, MGE_DA_FILTER_UCAST(i), reg_val); in mge_set_prom_mode()
1080 volatile uint32_t reg_val; in mge_init_locked() local
1135 reg_val = mge_set_port_serial_control(media_status); in mge_init_locked()
[all …]
/freebsd/sys/dev/qat/qat_hw/qat_200xx/
H A Dadf_drv.c86 unsigned int i = 0, bar_nr = 0, reg_val = 0; in adf_attach() local
135 reg_val = pci_read_config(dev, ADF_200XX_PFIEERRUNCSTSR, 4); in adf_attach()
136 if (reg_val) { in adf_attach()
140 reg_val); in adf_attach()
141 pci_write_config(dev, ADF_200XX_PFIEERRUNCSTSR, reg_val, 4); in adf_attach()
/freebsd/contrib/llvm-project/lldb/source/Core/
H A DDumpRegisterValue.cpp61 void lldb_private::DumpRegisterValue(const RegisterValue &reg_val, Stream &s, in DumpRegisterValue() argument
69 if (!reg_val.GetData(data)) in DumpRegisterValue()
135 dump_type_value(fields_type, reg_val.GetAsUInt32(), exe_scope, reg_info, in DumpRegisterValue()
138 dump_type_value(fields_type, reg_val.GetAsUInt64(), exe_scope, reg_info, in DumpRegisterValue()
/freebsd/sys/dev/cxgb/common/
H A Dcxgb_ael1002.c90 struct reg_val { struct
99 static int set_phy_regs(struct cphy *phy, const struct reg_val *rv) in set_phy_regs() argument
526 static struct reg_val regs[] = { in ael2005_setup_sr_edc()
823 static struct reg_val regs[] = { in ael2005_setup_twinax_edc()
827 static struct reg_val preemphasis[] = { in ael2005_setup_twinax_edc()
1253 static struct reg_val regs0[] = { in ael2005_reset()
1263 static struct reg_val regs1[] = { in ael2005_reset()
1408 static struct reg_val regs[] = { in ael2020_setup_sr_edc()
1434 static struct reg_val uCclock40MHz[] = { in ael2020_setup_twinax_edc()
1440 static struct reg_val uCclockActivate[] = { in ael2020_setup_twinax_edc()
[all …]
/freebsd/sys/arm/mv/
H A Dgpio.c882 uint32_t reg_val; in mv_gpio_reg_set() local
884 reg_val = mv_gpio_reg_read(dev, reg); in mv_gpio_reg_set()
885 reg_val |= GPIO(pin); in mv_gpio_reg_set()
886 mv_gpio_reg_write(dev, reg, reg_val); in mv_gpio_reg_set()
892 uint32_t reg_val; in mv_gpio_reg_clear() local
894 reg_val = mv_gpio_reg_read(dev, reg); in mv_gpio_reg_clear()
895 reg_val &= ~(GPIO(pin)); in mv_gpio_reg_clear()
896 mv_gpio_reg_write(dev, reg, reg_val); in mv_gpio_reg_clear()
938 uint32_t reg, reg_val; in mv_gpio_polarity() local
948 reg_val = mv_gpio_reg_read(dev, reg) & GPIO(pin); in mv_gpio_polarity()
[all …]
/freebsd/sys/dev/e1000/
H A De1000_i210.c711 u32 wuc, mdicnfg, ctrl, ctrl_ext, reg_val; in e1000_pll_workaround_i210() local
720 reg_val = mdicnfg & ~E1000_MDICNFG_EXT_MDIO; in e1000_pll_workaround_i210()
721 E1000_WRITE_REG(hw, E1000_MDICNFG, reg_val); in e1000_pll_workaround_i210()
753 reg_val = (E1000_INVM_AUTOLOAD << 4) | (tmp_nvm << 16); in e1000_pll_workaround_i210()
754 E1000_WRITE_REG(hw, E1000_EEARBC_I210, reg_val); in e1000_pll_workaround_i210()
762 reg_val = (E1000_INVM_AUTOLOAD << 4) | (nvm_word << 16); in e1000_pll_workaround_i210()
763 E1000_WRITE_REG(hw, E1000_EEARBC_I210, reg_val); in e1000_pll_workaround_i210()
/freebsd/sys/dev/etherswitch/ar40xx/
H A Dar40xx_hw_mdio.c92 uint16_t mmd_num, uint16_t reg_id, uint16_t reg_val) in ar40xx_hw_phy_mmd_write() argument
104 reg_val); in ar40xx_hw_phy_mmd_write()

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