| /freebsd/sys/contrib/device-tree/Bindings/c6x/ |
| H A D | clocks.txt | 10 - compatible: "ti,c64x+pll"
13 "ti,c6455-pll"
14 "ti,c6457-pll"
15 "ti,c6472-pll"
16 "ti,c6474-pll"
24 - ti,c64x+pll-bypass-delay: CPU cycles to delay when entering bypass mode
26 - ti,c64x+pll-reset-delay: CPU cycles to delay after PLL reset
28 - ti,c64x+pll-lock-delay: CPU cycles to delay after PLL frequency change
33 compatible = "ti,c6472-pll", "ti,c64x+pll";
37 ti,c64x+pll-bypass-delay = <200>;
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | qca,ath79-pll.txt | 6 - compatible: has to be "qca,<soctype>-pll" and one of the following
8 - "qca,ar7100-pll"
9 - "qca,ar7240-pll"
10 - "qca,ar9130-pll"
11 - "qca,ar9330-pll"
12 - "qca,ar9340-pll"
13 - "qca,qca9550-pll"
24 pll-controller@18050000 {
25 compatible = "qca,ar9132-pll", "qca,ar9130-pll";
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| H A D | keystone-pll.txt | 13 - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"
15 - reg - pll control0 and pll multiplier registers
17 post-divider registers are applicable only for main pll clock
24 compatible = "ti,keystone,main-pll-clock";
33 compatible = "ti,keystone,pll-clock";
35 clock-output-names = "pa-pll-clk";
42 - compatible : shall be "ti,keystone,pll-mux-clock"
44 - reg - pll mux register
54 compatible = "ti,keystone,pll-mux-clock";
64 - compatible : shall be "ti,keystone,pll-divider-clock"
[all …]
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| H A D | silabs,si5351.txt | 30 - silabs,pll-source: pair of (number, source) for each pll. Allows
31 to overwrite clock source of pll A (number=0) or B (number=1).
49 - silabs,multisynth-source: source pll A(0) or B(1) of corresponding multisynth
51 - silabs,pll-master: boolean, multisynth can change pll frequency.
52 - silabs,pll-reset: boolean, clock output can reset its pll.
83 silabs,pll-source = <0 0>, <1 0>;
98 silabs,pll-master;
114 pll-master;
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| H A D | snps,hsdk-pll-clock.txt | 8 - compatible: should be "snps,hsdk-<name>-pll-clock"
9 "snps,hsdk-core-pll-clock"
10 "snps,hsdk-gp-pll-clock"
11 "snps,hsdk-hdmi-pll-clock"
24 compatible = "snps,hsdk-core-pll-clock";
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| H A D | vt8500.txt | 9 "via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock
10 "wm,wm8650-pll-clock" - for a WM8650 PLL clock
11 "wm,wm8750-pll-clock" - for a WM8750 PLL clock
12 "wm,wm8850-pll-clock" - for a WM8850 PLL clock
16 - reg : shall be the control register offset from PMC base for the pll clock.
23 be a pll output.
61 compatible = "wm,wm8650-pll-clock";
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| H A D | qoriq-clock.txt | 88 4 platform pll n=pll/(n+1). For example, when n=1,
117 * "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)
118 * "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)
125 * "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0)
126 * "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0)
129 clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
130 For "fsl,qoriq-core-pll-[1,2].0" clocks, the single
163 compatible = "fsl,qoriq-core-pll-1.0";
171 compatible = "fsl,qoriq-core-pll-1.0";
194 platform-pll: platform-pll@c00 {
[all …]
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| H A D | ti-keystone-pllctrl.txt | 1 * Device tree bindings for Texas Instruments keystone pll controller
3 The main pll controller used to drive theC66x CorePacs, the switch fabric,
12 - reg: contains offset/length value for pll controller
17 pllctrl: pll-controller@02310000 {
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| H A D | snps,pll-clock.txt | 8 - compatible: should be "snps,axs10x-<name>-pll-clock"
9 "snps,axs10x-arc-pll-clock"
10 "snps,axs10x-pgu-pll-clock"
24 compatible = "snps,axs10x-arc-pll-clock";
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| H A D | sprd,sc9860-clk.txt | 7 - "sprd,sc9860-pll"
50 pll: pll {
51 compatible = "sprd,sc9860-pll";
60 clocks = <&ext_26m>, <&pll 0>,
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| /freebsd/sys/contrib/device-tree/Bindings/sound/ |
| H A D | pcm512x.txt | 20 is absent the device will be configured to clock from BCLK. If pll-in
21 and pll-out are specified in addition to a clock, the device is
24 - pll-in, pll-out : gpio pins used to connect the pll using <1>
26 given pll-in pin and PLL output on the given pll-out pin. An
27 external connection from the pll-out pin to the SCLK pin is assumed.
51 pll-in = <3>;
52 pll-out = <6>;
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| /freebsd/contrib/bc/tests/ |
| H A D | all.sh | 48 pll=1
53 n) pll=0 ; set -e ;;
148 if [ "$pll" -ne 0 ]; then
158 if [ "$pll" -ne 0 ]; then
166 if [ "$pll" -ne 0 ]; then
176 if [ "$pll" -ne 0 ]; then
191 if [ "$pll" -ne 0 ]; then
200 if [ "$pll" -ne 0 ]; then
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| H A D | scripts.sh | 50 pll=1
55 n) pll=0 ; set -e ;;
116 if [ "$pll" -ne 0 ]; then
127 if [ "$pll" -ne 0 ]; then
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| /freebsd/sys/contrib/device-tree/src/arm64/qcom/ |
| H A D | sa8295p-adp.dts | 366 vdda-pll-supply = <&vreg_l3g>;
382 vdda-pll-supply = <&vreg_l3g>;
402 vdda-pll-supply = <&vreg_l3g>;
418 vdda-pll-supply = <&vreg_l3g>;
434 vdda-pll-supply = <&vreg_l3g>;
450 vdda-pll-supply = <&vreg_l3g>;
467 vdda-pll-supply = <&vreg_l3a>;
486 vdda-pll-supply = <&vreg_l3a>;
503 vdda-pll-supply = <&vreg_l3a>;
520 vdda-pll-supply = <&vreg_l3a>;
[all …]
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| /freebsd/sys/contrib/device-tree/src/mips/qca/ |
| H A D | ar9132.dtsi | 17 clocks = <&pll ATH79_CLK_CPU>;
64 clocks = <&pll ATH79_CLK_AHB>;
89 pll: pll-controller@18050000 { label
90 compatible = "qca,ar9132-pll",
91 "qca,ar9130-pll";
107 clocks = <&pll ATH79_CLK_AHB>;
151 clocks = <&pll ATH79_CLK_AHB>;
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| H A D | ar9331.dtsi | 17 clocks = <&pll ATH79_CLK_CPU>;
90 pll: pll-controller@18050000 { label
91 compatible = "qca,ar9330-pll";
126 clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>;
141 clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>;
280 clocks = <&pll ATH79_CLK_AHB>;
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| /freebsd/sys/contrib/device-tree/Bindings/usb/ |
| H A D | nvidia,tegra124-xusb.txt | 49 - avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8 V.
50 - avdd-pll-erefe-supply: PLLE reference PLL power supply. Must supply 1.05 V.
51 - avdd-usb-ss-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V.
53 - hvdd-usb-ss-pll-e-supply: High-voltage PLLE power supply. Must supply 3.3 V.
59 - avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8 V.
60 - avdd-pll-uerefe-supply: PLLE reference PLL power supply. Must supply 1.05 V.
61 - dvdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V.
62 - hvdd-pex-pll-e-supply: High-voltage PLLE power supply. Must supply 1.8 V.
127 avdd-pll-utmip-supply = <&vddio_1v8>;
128 avdd-pll-erefe-supply = <&avdd_1v05_run>;
[all …]
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| /freebsd/sys/contrib/device-tree/src/c6x/ |
| H A D | tms320c6457.dtsi | 62 compatible = "ti,c6457-pll", "ti,c64x+pll";
64 ti,c64x+pll-bypass-delay = <300>;
65 ti,c64x+pll-reset-delay = <24000>;
66 ti,c64x+pll-lock-delay = <50000>;
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| H A D | tms320c6474.dtsi | 83 compatible = "ti,c6474-pll", "ti,c64x+pll";
85 ti,c64x+pll-bypass-delay = <120>;
86 ti,c64x+pll-reset-delay = <30000>;
87 ti,c64x+pll-lock-delay = <60000>;
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| H A D | tms320c6455.dtsi | 72 compatible = "ti,c6455-pll", "ti,c64x+pll";
74 ti,c64x+pll-bypass-delay = <1440>;
75 ti,c64x+pll-reset-delay = <15360>;
76 ti,c64x+pll-lock-delay = <24000>;
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| H A D | tms320c6472.dtsi | 106 compatible = "ti,c6472-pll", "ti,c64x+pll";
108 ti,c64x+pll-bypass-delay = <200>;
109 ti,c64x+pll-reset-delay = <12000>;
110 ti,c64x+pll-lock-delay = <80000>;
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| /freebsd/sys/contrib/device-tree/Bindings/display/ti/ |
| H A D | ti,omap5-dss.txt | 64 - reg: addresses and lengths of the register spaces for 'proto', 'phy' and 'pll'
65 - reg-names: "proto", "phy", "pll"
69 - clocks: handles to fclk and pll clock
86 - reg: addresses and lengths of the register spaces for 'wp', 'pll', 'phy',
88 - reg-names: "wp", "pll", "phy", "core"
92 - clocks: handles to fclk and pll clock
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| H A D | ti,dra7-dss.txt | 25 - clocks: handle to video1 pll clock and video2 pll clock
60 - reg: addresses and lengths of the register spaces for 'wp', 'pll', 'phy',
62 - reg-names: "wp", "pll", "phy", "core"
66 - clocks: handles to fclk and pll clock
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| H A D | ti,omap4-dss.txt | 83 - reg: addresses and lengths of the register spaces for 'proto', 'phy' and 'pll'
84 - reg-names: "proto", "phy", "pll"
88 - clocks: handles to fclk and pll clock
105 - reg: addresses and lengths of the register spaces for 'wp', 'pll', 'phy',
107 - reg-names: "wp", "pll", "phy", "core"
111 - clocks: handles to fclk and pll clock
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| /freebsd/sys/contrib/device-tree/Bindings/clock/st/ |
| H A D | st,clkgen.txt | 4 A Clockgen node can contain pll, diviser or multiplexer nodes.
35 [4] Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
49 clk_s_a0_pll: clk-s-a0-pll {
55 clock-output-names = "clk-s-a0-pll-ofd-0";
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