Home
last modified time | relevance | path

Searched refs:no_shift (Results 1 – 11 of 11) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFastISel.cpp2717 /* 1 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 31 }, in ARMEmitIntExt()
2718 /* 1 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 31 } }, in ARMEmitIntExt()
2719 /* 8 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 24 }, in ARMEmitIntExt()
2720 /* 8 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 24 } }, in ARMEmitIntExt()
2721 /* 16 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 16 }, in ARMEmitIntExt()
2722 /* 16 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 16 } } in ARMEmitIntExt()
2727 /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 }, in ARMEmitIntExt()
2728 /* 1 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 1 } }, in ARMEmitIntExt()
2729 /* 8 bit sext */ { { ARM::SXTB , 0, ARM_AM::no_shift, 0 }, in ARMEmitIntExt()
2730 /* 8 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 255 } }, in ARMEmitIntExt()
[all …]
H A DARMSelectionDAGInfo.h25 default: return ARM_AM::no_shift; in getShiftOpcForNode()
H A DARMISelDAGToDAG.cpp618 if (ShOpcVal == ARM_AM::no_shift) return false; in SelectImmShifterOperand()
642 if (ShOpcVal == ARM_AM::no_shift) return false; in SelectRegShifterOperand()
767 if (ShOpcVal != ARM_AM::no_shift) { in SelectLdStSOReg()
777 ShOpcVal = ARM_AM::no_shift; in SelectLdStSOReg()
780 ShOpcVal = ARM_AM::no_shift; in SelectLdStSOReg()
785 if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift && in SelectLdStSOReg()
789 if (ShOpcVal != ARM_AM::no_shift) { in SelectLdStSOReg()
800 ShOpcVal = ARM_AM::no_shift; in SelectLdStSOReg()
803 ShOpcVal = ARM_AM::no_shift; in SelectLdStSOReg()
842 if (ShOpcVal != ARM_AM::no_shift) { in SelectAddrMode2OffsetReg()
[all …]
H A DARMSchedule.td168 class CheckAM2NoShift<int n> : CheckImmOperand_s<n, "ARM_AM::no_shift">;
H A DARMLoadStoreOptimizer.cpp1553 int Imm = ARM_AM::getAM2Opc(AddSub, abs(Offset), ARM_AM::no_shift); in MergeBaseUpdateLoadStore()
1583 int Imm = ARM_AM::getAM2Opc(AddSub, abs(Offset), ARM_AM::no_shift); in MergeBaseUpdateLoadStore()
H A DARMFrameLowering.cpp1823 MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::add, 4, ARM_AM::no_shift)); in emitPopInst()
H A DARMISelLowering.cpp4874 } else if ((ARM_AM::getShiftOpcForNode(LHS.getOpcode()) != ARM_AM::no_shift) && in getARMCmp()
4875 (ARM_AM::getShiftOpcForNode(RHS.getOpcode()) == ARM_AM::no_shift)) { in getARMCmp()
19759 if (ShOpcVal != ARM_AM::no_shift) { in getARMIndexedAddressParts()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMAddressingModes.h28 no_shift = 0, enumerator
H A DARMMCCodeEmitter.cpp248 case ARM_AM::no_shift: in getShiftOp()
H A DARMInstPrinter.cpp52 if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm)) in printRegImmShift()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp1481 return isPostIdxRegShifted() && PostIdxReg.ShiftTy == ARM_AM::no_shift; in isPostIdxReg()
1647 if (Memory.ShiftType != ARM_AM::no_shift) return false; in isAddrMode3()
1716 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) in isMemTBB()
1740 if (Memory.ShiftType == ARM_AM::no_shift) in isT2MemRegOffset()
1751 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) in isMemThumbRR()
1917 if (shift == 0 && Memory.ShiftType != ARM_AM::no_shift) in isMemRegRQOffset()
3017 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); in addAddrMode2Operands()
3040 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); in addAM2OffsetImmOperands()
4049 if (Memory.ShiftType != ARM_AM::no_shift) { in print()
4060 if (PostIdxReg.ShiftTy != ARM_AM::no_shift) in print()
[all …]