Lines Matching refs:no_shift
2651 /* 1 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 31 }, in ARMEmitIntExt()
2652 /* 1 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 31 } }, in ARMEmitIntExt()
2653 /* 8 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 24 }, in ARMEmitIntExt()
2654 /* 8 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 24 } }, in ARMEmitIntExt()
2655 /* 16 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 16 }, in ARMEmitIntExt()
2656 /* 16 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 16 } } in ARMEmitIntExt()
2661 /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 }, in ARMEmitIntExt()
2662 /* 1 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 1 } }, in ARMEmitIntExt()
2663 /* 8 bit sext */ { { ARM::SXTB , 0, ARM_AM::no_shift, 0 }, in ARMEmitIntExt()
2664 /* 8 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 255 } }, in ARMEmitIntExt()
2665 /* 16 bit sext */ { { ARM::SXTH , 0, ARM_AM::no_shift, 0 }, in ARMEmitIntExt()
2666 /* 16 bit zext */ { ARM::UXTH , 0, ARM_AM::no_shift, 0 } } in ARMEmitIntExt()
2669 /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 }, in ARMEmitIntExt()
2670 /* 1 bit zext */ { ARM::t2ANDri, 1, ARM_AM::no_shift, 1 } }, in ARMEmitIntExt()
2671 /* 8 bit sext */ { { ARM::t2SXTB , 0, ARM_AM::no_shift, 0 }, in ARMEmitIntExt()
2672 /* 8 bit zext */ { ARM::t2ANDri, 1, ARM_AM::no_shift, 255 } }, in ARMEmitIntExt()
2673 /* 16 bit sext */ { { ARM::t2SXTH , 0, ARM_AM::no_shift, 0 }, in ARMEmitIntExt()
2674 /* 16 bit zext */ { ARM::t2UXTH , 0, ARM_AM::no_shift, 0 } } in ARMEmitIntExt()
2699 assert(((Shift == ARM_AM::no_shift) == (Opc != ARM::MOVsi)) && in ARMEmitIntExt()
2710 bool ImmIsSO = (Shift != ARM_AM::no_shift); in ARMEmitIntExt()