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Searched refs:isReg (Results 1 – 25 of 463) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsInstPrinter.cpp32 static bool isReg(const MCInst &MI, unsigned OpNo) { in isReg() function
33 assert(MI.getOperand(OpNo).isReg() && "Register operand expected."); in isReg()
131 if (Op.isReg()) { in printOperand()
277 return (isReg<Mips::ZERO>(MI, 0) && isReg<Mips::ZERO>(MI, 1) && in printAlias()
279 (isReg<Mips::ZERO>(MI, 1) && in printAlias()
283 return isReg<Mips::ZERO_64>(MI, 1) && in printAlias()
288 return isReg<Mips::ZERO>(MI, 1) && in printAlias()
292 return isReg<Mips::ZERO_64>(MI, 1) && in printAlias()
296 return isReg<Mips::ZERO>(MI, 0) && in printAlias()
300 return isReg<Mips::FCC0>(MI, 0) && in printAlias()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineOperand.h227 return isReg() ? 0 : SubReg_TargetFlags; in getTargetFlags()
230 assert(!isReg() && "Register operands can't have target flags"); in setTargetFlags()
235 assert(!isReg() && "Register operands can't have target flags"); in addTargetFlag()
328 bool isReg() const { return OpKind == MO_Register; } in isReg() function
369 assert(isReg() && "This is not a register operand!"); in getReg()
374 assert(isReg() && "Wrong MachineOperand accessor"); in getSubReg()
379 assert(isReg() && "Wrong MachineOperand accessor"); in isUse()
384 assert(isReg() && "Wrong MachineOperand accessor"); in isDef()
389 assert(isReg() && "Wrong MachineOperand accessor"); in isImplicit()
394 assert(isReg() && "Wrong MachineOperand accessor"); in isDead()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIOptimizeExecMasking.cpp123 if (Src.isReg() && Src.getReg() == Exec) in isCopyFromExec()
138 if (Dst.isReg() && Dst.getReg() == Exec && MI.getOperand(1).isReg()) in isCopyToExec()
163 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC) in isLogicalOpOnExec()
166 if (Src2.isReg() && Src2.getReg() == AMDGPU::EXEC) in isLogicalOpOnExec()
179 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC_LO) in isLogicalOpOnExec()
182 if (Src2.isReg() && Src2.getReg() == AMDGPU::EXEC_LO) in isLogicalOpOnExec()
235 bool RegSrc = MI.getOperand(1).isReg(); in removeTerminatorBit()
240 bool RegSrc = MI.getOperand(1).isReg(); in removeTerminatorBit()
379 if (MO.isReg() && MO.isKill()) { in findInstrBackwards()
560 if (Src0.isReg() && Src0.getReg() == CopyFromExec) { in optimizeExecSequence()
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H A DSIPeepholeSDWA.cpp105 assert(Target->isReg()); in SDWAOperand()
106 assert(Replaced->isReg()); in SDWAOperand()
271 assert(To.isReg() && From.isReg()); in copyRegOperand()
283 return LHS.isReg() && in isSameReg()
284 RHS.isReg() && in isSameReg()
291 if (!Reg->isReg() || !Reg->isDef()) in findSingleRegUse()
313 if (!Reg->isReg()) in findSingleRegDef()
321 if (DefMO.isReg() && DefMO.getReg() == Reg->getReg()) in findSingleRegDef()
392 if (!Reg->isReg() || !Reg->isDef()) in potentialToConvert()
457 assert(Src && (Src->isReg() || Src->isImm())); in convertToSDWA()
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H A DSIShrinkInstructions.cpp104 if (Src0.isReg()) { in foldImmediates()
155 if (MO.isReg()) { in shouldShrinkTrue16()
239 if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask()) in copyExtraImplicitOps()
250 if (!MI.getOperand(0).isReg()) in shrinkScalarCompare()
255 if (!Src0.isReg()) in shrinkScalarCompare()
384 if (MI.getOperand(i).isReg() && MI.getOperand(i).isTied() && in shrinkMIMG()
437 if (Src1.isReg() && TRI->isVGPR(*MRI, Src1.getReg())) in shrinkMadFma()
439 else if (Src0.isReg() && TRI->isVGPR(*MRI, Src0.getReg())) in shrinkMadFma()
474 if (Src2.isReg() && TRI->isVGPR(*MRI, Src2.getReg())) { in shrinkMadFma()
578 if (Dest->getReg().isVirtual() && SrcReg->isReg()) { in shrinkScalarLogicOp()
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H A DSIFoldOperands.cpp59 assert(FoldOp.isReg() || FoldOp.isGlobal()); in FoldableDef()
78 bool isReg() const { return Kind == MachineOperand::MO_Register; } in isReg() function
81 assert(isReg()); in getReg()
86 assert(isReg()); in getSubReg()
165 bool isReg() const { return Def.isReg(); } in isReg() function
611 assert(Old.isReg()); in updateOperand()
836 if (!Op.isReg() || !CommutedOp.isReg()) in tryAddToFoldList()
841 if (Op.isReg() && CommutedOp.isReg() && in tryAddToFoldList()
861 if (!OtherOp.isReg() || in tryAddToFoldList()
908 if (!SrcOp.isReg() || SrcOp.getReg().isPhysical()) in lookUpCopyChain()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiMCCodeEmitter.cpp111 if (MCOp.isReg()) in getMachineOpValue()
145 (Op2.isReg() && Op2.getReg() != Lanai::R0) || (Op2.isExpr()))) in adjustPqBits()
149 assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && in adjustPqBits()
153 (Op2.isReg() && Op2.getReg() != Lanai::R0))) in adjustPqBits()
191 assert(Op1.isReg() && "First operand is not register."); in getRiMemoryOpValue()
223 assert(Op1.isReg() && "First operand is not register."); in getRrMemoryOpValue()
225 assert(Op2.isReg() && "Second operand is not register."); in getRrMemoryOpValue()
262 assert(Op1.isReg() && "First operand is not register."); in getSplsOpValue()
290 if (MCOp.isReg() || MCOp.isImm()) in getBranchTargetOpValue()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCMacroFusion.cpp74 if (!Op1.isReg() || !Op2.isReg()) in matchingRegOps()
106 if (!RA.isReg()) in checkOpConstraints()
115 if (!RT.isReg()) in checkOpConstraints()
172 if (!BT.isReg() || (!BT.getReg().isVirtual() && BT.getReg() != PPC::CR0)) in checkOpConstraints()
183 if (!BT.isReg() || (!BT.getReg().isVirtual() && BT.getReg() != PPC::CR0)) in checkOpConstraints()
207 if (!SI.isImm() || !RA.isReg()) in checkOpConstraints()
218 if (!SI.isImm() || !RA.isReg()) in checkOpConstraints()
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiDelaySlotFiller.cpp106 assert(RI->getOpcode() == Lanai::LDW_RI && RI->getOperand(0).isReg() && in runOnMachineBasicBlock()
108 RI->getOperand(1).isReg() && in runOnMachineBasicBlock()
113 RI->getOperand(0).isReg() && in runOnMachineBasicBlock()
115 RI->getOperand(1).isReg() && in runOnMachineBasicBlock()
204 if (!MO.isReg() || !(Reg = MO.getReg())) in delayHasHazard()
233 if (!MO.isReg() || !(Reg = MO.getReg())) in insertDefsUses()
H A DLanaiMemAluCombiner.cpp178 return ((Op.isReg() && Op.getReg() == Lanai::R0) || in isZeroOperand()
240 assert((AluOffset.isReg() || AluOffset.isImm()) && in insertMergedInstruction()
257 if (AluOffset.isReg()) in insertMergedInstruction()
300 if (Offset.isReg() && Offset.getReg() == Lanai::R0) in isSuitableAluInstr()
311 } else if (Op2.isReg()) { in isSuitableAluInstr()
313 if (Offset.isReg() && Op2.getReg() == Offset.getReg()) in isSuitableAluInstr()
349 if (Offset->isReg() && InstrUsesReg(First, Offset)) in findClosestSuitableAluInstr()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineInstr.cpp173 if (MO.isReg()) in removeRegOperandsFromUseLists()
179 if (MO.isReg()) in addRegOperandsToUseLists()
228 bool isImpReg = Op.isReg() && Op.isImplicit(); in addOperand()
230 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) { in addOperand()
268 if (NewMO->isReg()) { in addOperand()
303 if (Operands[i].isReg()) in removeOperand()
308 if (MRI && Operands[OpNo].isReg()) in removeOperand()
689 if (!MO.isReg()) { in isIdenticalTo()
802 [Reg](Operand &Op) { return Op.isReg() && Op.getReg() == Reg; }); in getDebugOperandsForRegHelper()
830 if (MO.isReg() && MO.isImplicit()) in getNumExplicitOperands()
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H A DMIRCanonicalizerPass.cpp155 if (!MO.isReg()) in rescheduleCanonically()
175 if (!MO.isReg() || !MO.getReg().isVirtual()) in rescheduleCanonically()
187 if (II->getOperand(i).isReg()) { in rescheduleCanonically()
302 if (!MI->getOperand(0).isReg()) in propagateLocalCopies()
304 if (!MI->getOperand(1).isReg()) in propagateLocalCopies()
342 if (!MO.isReg()) in doDefKillClear()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyDebugFixup.cpp68 if (MI.isDebugValue() && MI.getDebugOperand(0).isReg() && in setDanglingDebugValuesUndef()
97 if (MO.isReg() && MO.getReg().isValid() && in runOnMachineFunction()
124 if (MO.isReg() && MFI.isVRegStackified(MO.getReg())) { in runOnMachineFunction()
145 if (MO.isReg() && MFI.isVRegStackified(MO.getReg())) { in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonExpandCondsets.cpp308 if (!Op.isReg() || !Op.isUse() || Op.getReg() != Reg || in updateKillFlags()
361 if (!Op.isReg() || !Op.isDef()) in updateDeadsInRange()
485 if (!Op.isReg() || !DefRegs.count(Op)) in updateDeadsInRange()
587 if (SO.isReg()) { in getCondTfrOpcode()
646 if (SrcOp.isReg()) { in genCondTfrFor()
685 if (Op.isReg()) in split()
695 if (ST.isReg() && SF.isReg()) { in split()
735 if (!Op.isReg() || !Op.isDef()) in isPredicable()
773 if (!Op.isReg() || !Op.isDef()) in getReachingDefForPred()
807 if (!Op.isReg()) in canMoveOver()
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H A DHexagonVLIWPacketizer.cpp144 if (!MO.isReg() || !MO.isDef()) in hasWriteToReadDep()
311 if (MO.isReg() && MO.getReg() == DepReg && !MO.isImplicit()) in isCallDependent()
386 if (MO.isReg() && MO.getReg() == MI->getOperand(0).getReg()) in cleanUpDotCur()
428 if (MO.isReg() && MO.getReg() == DestReg) in canPromoteToDotCur()
576 if (MO.isReg() && MO.isDef()) in getPostIncrementOperand()
580 if (MO.isReg() && MO.isUse() && DefRegsSet.count(MO.getReg())) in getPostIncrementOperand()
586 assert(Op1.isReg() && "Post increment operand has be to a register."); in getPostIncrementOperand()
592 assert(Op0.isReg() && "Post increment operand has be to a register."); in getPostIncrementOperand()
650 if (Val.isReg() && Val.getReg() != DepReg) in canPromoteToNewValueStore()
703 if (!MO.isReg()) in canPromoteToNewValueStore()
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H A DHexagonHardwareLoops.cpp336 bool isReg() const { return Kind == CV_Register; } in isReg() function in __anoncd4cffa40111::CountValue
340 assert(isReg() && "Wrong CountValue accessor"); in getReg()
345 assert(isReg() && "Wrong CountValue accessor"); in getSubReg()
355 if (isReg()) { OS << printReg(Contents.R.Reg, TRI, Contents.R.Sub); } in print()
674 if (Op1.isReg()) { in getLoopTripCount()
694 if (InitialValue->isReg()) { in getLoopTripCount()
704 if (EndValue->isReg()) { in getLoopTripCount()
739 if (Start->isReg()) { in computeCount()
745 if (End->isReg()) { in computeCount()
752 if (!Start->isReg() && !Start->isImm()) in computeCount()
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H A DHexagonNewValueJump.cpp143 if (!Op.isReg() || !Op.isDef()) in INITIALIZE_PASS_DEPENDENCY()
168 if (II->getOperand(i).isReg() && in INITIALIZE_PASS_DEPENDENCY()
553 if (foundJump && !foundCompare && MI.getOperand(0).isReg() && in runOnMachineFunction()
560 isSecondOpReg = MI.getOperand(2).isReg(); in runOnMachineFunction()
589 if (MI.getOperand(0).isReg() && MI.getOperand(0).isDef() && in runOnMachineFunction()
640 if (!MO.isReg() || !MO.isUse()) in runOnMachineFunction()
647 if (!Op.isReg() || !Op.isUse() || !Op.isKill()) in runOnMachineFunction()
693 if (cmpInstr->getOperand(0).isReg() && in runOnMachineFunction()
696 if (cmpInstr->getOperand(1).isReg() && in runOnMachineFunction()
H A DHexagonSplitDouble.cpp173 if (MI->getOperand(1).isReg()) in isFixedInstr()
178 if (MI->getOperand(0).isReg()) in isFixedInstr()
205 if (!Op.isReg()) in isFixedInstr()
252 if (&MO == &Op || !MO.isReg() || MO.getSubReg()) in partitionRegisters()
435 if (Op.isReg() && Part.count(Op.getReg())) in isProfitable()
492 assert(Cond[1].isReg() && "Unexpected Cond vector from analyzeBranch"); in collectIndRegsForLoop()
589 if (!Op.isReg()) { in createHalfInstr()
693 assert(Op0.isReg() && Op1.isImm()); in splitImmediate()
721 assert(Op0.isReg()); in splitCombine()
729 if (!Op1.isReg()) { in splitCombine()
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H A DHexagonGenMux.cpp162 if (!MO.isReg() || MO.isImplicit()) in getDefsUses()
199 bool IsReg1 = Src1.isReg(), IsReg2 = Src2.isReg(); in getMuxOpcode()
291 Register SR1 = Src1->isReg() ? Src1->getReg() : Register(); in genMuxInBlock()
292 Register SR2 = Src2->isReg() ? Src2->getReg() : Register(); in genMuxInBlock()
350 if (!Op.isReg() || !Op.isUse()) in genMuxInBlock()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVRedundantCopyElimination.cpp76 if (Opc == RISCV::BEQ && Cond[2].isReg() && Cond[2].getReg() == RISCV::X0 && in guaranteesZeroRegInBlock()
79 if (Opc == RISCV::BNE && Cond[2].isReg() && Cond[2].getReg() == RISCV::X0 && in guaranteesZeroRegInBlock()
116 if (MI->isCopy() && MI->getOperand(0).isReg() && in optimizeBlock()
117 MI->getOperand(1).isReg()) { in optimizeBlock()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXProxyRegErasure.cpp67 assert(InOp.isReg() && "ProxyReg input should be a register."); in runOnMachineFunction()
68 assert(OutOp.isReg() && "ProxyReg output should be a register."); in runOnMachineFunction()
94 if (!Op.isReg()) in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/AsmParser/
H A DM68kAsmParser.cpp156 bool isReg() const override;
313 bool M68kOperand::isReg() const { in isReg() function in M68kOperand
318 assert(isReg()); in getReg()
323 assert(isReg() && "wrong operand kind"); in addRegOperands()
549 return isReg() && checkRegisterClass(getReg(), in isAReg()
555 return isReg() && checkRegisterClass(getReg(), in isDReg()
561 return isReg() && checkRegisterClass(getReg(), in isFPDReg()
568 return isReg() && checkRegisterClass(getReg(), in isFPCReg()
581 if (Operand.isReg() && in validateTargetOperandClass()
589 if (Operand.isReg() && in validateTargetOperandClass()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCMCCodeEmitter.cpp61 if (MO.isReg() || MO.isImm()) in getDirectBrEncoding()
169 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getCondBrEncoding()
181 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsDirectBrEncoding()
193 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsCondBrEncoding()
204 assert(MI.getOperand(OpNo).isReg() && "Operand should be a register"); in getVSRpEvenEncoding()
214 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getImm16Encoding()
226 assert(!MO.isReg() && "Not expecting a register for this operand."); in getImm34Encoding()
426 if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups, STI); in getTLSRegEncoding()
481 if (MO.isReg()) { in getMachineOpValue()
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/
H A DSparcInstPrinter.cpp68 if (!MI->getOperand(0).isReg()) in printSparcAliasInstr()
92 || (!MI->getOperand(0).isReg()) in printSparcAliasInstr()
118 if (MO.isReg()) { in printOperand()
156 if (Op1.isReg() && Op1.getReg() != SP::G0) { in printMemOperand()
164 PrintedFirstOperand && ((Op2.isReg() && Op2.getReg() == SP::G0) || in printMemOperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86AvoidStoreForwardingBlocks.cpp319 if (!((Base.isReg() && Base.getReg() != X86::NoRegister) || Base.isFI())) in isRelevantAddressingMode()
325 if (!(Index.isReg() && Index.getReg() == X86::NoRegister)) in isRelevantAddressingMode()
327 if (!(Segment.isReg() && Segment.getReg() == X86::NoRegister)) in isRelevantAddressingMode()
402 if (LoadBase.isReg()) in buildCopy()
422 if (StoreBase.isReg()) in buildCopy()
425 assert(StoreSrcVReg.isReg() && "Expected virtual register"); in buildCopy()
499 if (LoadBase.isReg()) { in updateKillStatus()
509 if (StoreBase.isReg()) { in updateKillStatus()
611 if (LoadBase.isReg() != StoreBase.isReg()) in hasSameBaseOpValue()
613 if (LoadBase.isReg()) in hasSameBaseOpValue()

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