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Searched refs:isReg (Results 1 – 25 of 447) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsInstPrinter.cpp32 static bool isReg(const MCInst &MI, unsigned OpNo) { in isReg()
33 assert(MI.getOperand(OpNo).isReg() && "Register operand expected."); in isReg()
131 if (Op.isReg()) { in printOperand()
277 return (isReg<Mips::ZERO>(MI, 0) && isReg<Mips::ZERO>(MI, 1) && in printAlias()
279 (isReg<Mips::ZERO>(MI, 1) && in printAlias()
283 return isReg<Mips::ZERO_64>(MI, 1) && in printAlias()
288 return isReg<Mips::ZERO>(MI, 1) && in printAlias()
292 return isReg<Mips::ZERO_64>(MI, 1) && in printAlias()
296 return isReg<Mip in printAlias()
31 static bool isReg(const MCInst &MI, unsigned OpNo) { isReg() function
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineOperand.h227 return isReg() ? 0 : SubReg_TargetFlags; in getTargetFlags()
230 assert(!isReg() && "Register operands can't have target flags"); in setTargetFlags()
235 assert(!isReg() && "Register operands can't have target flags"); in addTargetFlag()
328 /// isReg - Tests if this is a MO_Register operand.
329 bool isReg() const { return OpKind == MO_Register; } in isReg() function
370 assert(isReg() && "This is not a register operand!"); in getReg()
375 assert(isReg() && "Wrong MachineOperand accessor"); in getSubReg()
380 assert(isReg() && "Wrong MachineOperand accessor"); in isUse()
385 assert(isReg() && "Wrong MachineOperand accessor"); in isDef()
390 assert(isReg() in isImplicit()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIOptimizeExecMasking.cpp104 if (Src.isReg() && Src.getReg() == Exec) in isCopyFromExec()
119 if (Dst.isReg() && Dst.getReg() == Exec && MI.getOperand(1).isReg()) in isCopyToExec()
144 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC) in isLogicalOpOnExec()
147 if (Src2.isReg() && Src2.getReg() == AMDGPU::EXEC) in isLogicalOpOnExec()
160 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC_LO) in isLogicalOpOnExec()
163 if (Src2.isReg() && Src2.getReg() == AMDGPU::EXEC_LO) in isLogicalOpOnExec()
216 bool RegSrc = MI.getOperand(1).isReg(); in removeTerminatorBit()
221 bool RegSrc = MI.getOperand(1).isReg(); in removeTerminatorBit()
360 if (MO.isReg() && MO.isKill()) { in findInstrBackwards()
541 if (Src0.isReg() && Src0.getReg() == CopyFromExec) { in optimizeExecSequence()
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H A DSIPeepholeSDWA.cpp91 assert(Target->isReg()); in SDWAOperand()
92 assert(Replaced->isReg()); in SDWAOperand()
254 assert(To.isReg() && From.isReg()); in copyRegOperand()
266 return LHS.isReg() && in isSameReg()
267 RHS.isReg() && in isSameReg()
274 if (!Reg->isReg() || !Reg->isDef()) in findSingleRegUse()
296 if (!Reg->isReg()) in findSingleRegDef()
304 if (DefMO.isReg() && DefMO.getReg() == Reg->getReg()) in findSingleRegDef()
343 if (!Reg->isReg() || !Reg->isDef()) in potentialToConvert()
390 assert(Src && (Src->isReg() || Src->isImm())); in convertToSDWA()
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H A DSIShrinkInstructions.cpp97 if (Src0.isReg()) { in foldImmediates()
148 if (MO.isReg()) { in shouldShrinkTrue16()
228 if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask()) in copyExtraImplicitOps()
239 if (!MI.getOperand(0).isReg()) in shrinkScalarCompare()
244 if (!Src0.isReg()) in shrinkScalarCompare()
373 if (MI.getOperand(i).isReg() && MI.getOperand(i).isTied() && in shrinkMIMG()
427 if (Src1.isReg() && TRI->isVGPR(*MRI, Src1.getReg())) in shrinkMadFma()
429 else if (Src0.isReg() && TRI->isVGPR(*MRI, Src0.getReg())) in shrinkMadFma()
455 if (Src2.isReg() && TRI->isVGPR(*MRI, Src2.getReg())) { in shrinkMadFma()
550 if (Dest->getReg().isVirtual() && SrcReg->isReg()) { in shrinkScalarLogicOp()
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H A DSIFoldOperands.cpp47 assert(FoldOp->isReg() || FoldOp->isGlobal()); in FoldCandidate()
60 bool isReg() const { in isReg() function
208 assert(Old.isReg() && Fold.isImm()); in canUseImmWithOpSel()
360 assert(Old.isReg()); in updateOperand()
571 if (!MI->getOperand(OpNo).isReg() || !MI->getOperand(CommuteOpNo).isReg()) in tryAddToFoldList()
589 if (!OtherOp.isReg() || in tryAddToFoldList()
607 !OpToFold->isReg() && !TII->isInlineConstant(*OpToFold)) { in tryAddToFoldList()
610 if (!OpImm.isReg() && in tryAddToFoldList()
633 if (!OpToFold->isReg() && !TII->isInlineConstant(*OpToFold, OpInfo)) { in tryAddToFoldList()
637 if (OpNo != i && !Op.isReg() && in tryAddToFoldList()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiMCCodeEmitter.cpp113 if (MCOp.isReg()) in getMachineOpValue()
147 (Op2.isReg() && Op2.getReg() != Lanai::R0) || (Op2.isExpr()))) in adjustPqBits()
151 assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && in adjustPqBits()
155 (Op2.isReg() && Op2.getReg() != Lanai::R0))) in adjustPqBits()
193 assert(Op1.isReg() && "First operand is not register."); in getRiMemoryOpValue()
225 assert(Op1.isReg() && "First operand is not register."); in getRrMemoryOpValue()
227 assert(Op2.isReg() && "Second operand is not register."); in getRrMemoryOpValue()
264 assert(Op1.isReg() && "First operand is not register."); in getSplsOpValue()
292 if (MCOp.isReg() || MCO in getBranchTargetOpValue()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCMacroFusion.cpp74 if (!Op1.isReg() || !Op2.isReg()) in matchingRegOps()
106 if (!RA.isReg()) in checkOpConstraints()
115 if (!RT.isReg()) in checkOpConstraints()
172 if (!BT.isReg() || (!BT.getReg().isVirtual() && BT.getReg() != PPC::CR0)) in checkOpConstraints()
183 if (!BT.isReg() || (!BT.getReg().isVirtual() && BT.getReg() != PPC::CR0)) in checkOpConstraints()
207 if (!SI.isImm() || !RA.isReg()) in checkOpConstraints()
218 if (!SI.isImm() || !RA.isReg()) in checkOpConstraints()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineInstr.cpp171 if (MO.isReg()) in removeRegOperandsFromUseLists()
177 if (MO.isReg()) in addRegOperandsToUseLists()
226 bool isImpReg = Op.isReg() && Op.isImplicit(); in addOperand()
228 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) { in addOperand()
266 if (NewMO->isReg()) { in addOperand()
301 if (Operands[i].isReg()) in removeOperand()
306 if (MRI && Operands[OpNo].isReg()) in removeOperand()
682 if (!MO.isReg()) { in isIdenticalTo()
802 if (MO.isReg() && MO.isImplicit()) in getNumExplicitOperands()
816 if (!MO.isReg() || !MO.isDef() || MO.isImplicit()) in getNumExplicitDefs()
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H A DMIRCanonicalizerPass.cpp155 if (!MO.isReg()) in rescheduleCanonically()
175 if (!MO.isReg() || !MO.getReg().isVirtual()) in rescheduleCanonically()
187 if (II->getOperand(i).isReg()) { in rescheduleCanonically()
302 if (!MI->getOperand(0).isReg()) in propagateLocalCopies()
304 if (!MI->getOperand(1).isReg()) in propagateLocalCopies()
342 if (!MO.isReg()) in doDefKillClear()
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiDelaySlotFiller.cpp107 assert(RI->getOpcode() == Lanai::LDW_RI && RI->getOperand(0).isReg() && in runOnMachineBasicBlock()
109 RI->getOperand(1).isReg() && in runOnMachineBasicBlock()
114 RI->getOperand(0).isReg() && in runOnMachineBasicBlock()
116 RI->getOperand(1).isReg() && in runOnMachineBasicBlock()
205 if (!MO.isReg() || !(Reg = MO.getReg())) in delayHasHazard()
234 if (!MO.isReg() || !(Reg = MO.getReg())) in insertDefsUses()
H A DLanaiMemAluCombiner.cpp184 return ((Op.isReg() && Op.getReg() == Lanai::R0) || in isZeroOperand()
246 assert((AluOffset.isReg() || AluOffset.isImm()) && in insertMergedInstruction()
263 if (AluOffset.isReg()) in insertMergedInstruction()
306 if (Offset.isReg() && Offset.getReg() == Lanai::R0) in isSuitableAluInstr()
317 } else if (Op2.isReg()) { in isSuitableAluInstr()
319 if (Offset.isReg() && Op2.getReg() == Offset.getReg()) in isSuitableAluInstr()
355 if (Offset->isReg() && InstrUsesReg(First, Offset)) in findClosestSuitableAluInstr()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyDebugFixup.cpp71 if (MI.isDebugValue() && MI.getDebugOperand(0).isReg() && in setDanglingDebugValuesUndef()
100 if (MO.isReg() && MO.getReg().isValid() && in runOnMachineFunction()
127 if (MO.isReg() && MFI.isVRegStackified(MO.getReg())) { in runOnMachineFunction()
148 if (MO.isReg() && MFI.isVRegStackified(MO.getReg())) { in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonHardwareLoops.cpp343 bool isReg() const { return Kind == CV_Register; } in isReg() function in __anoncd4cffa40111::CountValue
347 assert(isReg() && "Wrong CountValue accessor"); in getReg()
352 assert(isReg() && "Wrong CountValue accessor"); in getSubReg()
362 if (isReg()) { OS << printReg(Contents.R.Reg, TRI, Contents.R.Sub); } in print()
681 if (Op1.isReg()) { in getLoopTripCount()
701 if (InitialValue->isReg()) { in getLoopTripCount()
711 if (EndValue->isReg()) { in getLoopTripCount()
741 if (Start->isReg()) { in computeCount()
747 if (End->isReg()) { in computeCount()
754 if (!Start->isReg() && !Start->isImm()) in computeCount()
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H A DHexagonExpandCondsets.cpp324 if (!Op.isReg() || !Op.isUse() || Op.getReg() != Reg || in updateKillFlags()
377 if (!Op.isReg() || !Op.isDef()) in updateDeadsInRange()
502 if (!Op.isReg() || !DefRegs.count(Op)) in updateDeadsInRange()
604 if (SO.isReg()) { in getCondTfrOpcode()
663 if (SrcOp.isReg()) { in genCondTfrFor()
702 if (Op.isReg()) in split()
712 if (ST.isReg() && SF.isReg()) { in split()
752 if (!Op.isReg() || !Op.isDef()) in isPredicable()
790 if (!Op.isReg() || !Op.isDef()) in getReachingDefForPred()
824 if (!Op.isReg()) in canMoveOver()
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H A DHexagonVLIWPacketizer.cpp152 if (!MO.isReg() || !MO.isDef()) in hasWriteToReadDep()
320 if (MO.isReg() && MO.getReg() == DepReg && !MO.isImplicit()) in isCallDependent()
395 if (MO.isReg() && MO.getReg() == MI->getOperand(0).getReg()) in cleanUpDotCur()
437 if (MO.isReg() && MO.getReg() == DestReg) in canPromoteToDotCur()
585 if (MO.isReg() && MO.isDef()) in getPostIncrementOperand()
589 if (MO.isReg() && MO.isUse() && DefRegsSet.count(MO.getReg())) in getPostIncrementOperand()
595 assert(Op1.isReg() && "Post increment operand has be to a register."); in getPostIncrementOperand()
601 assert(Op0.isReg() && "Post increment operand has be to a register."); in getPostIncrementOperand()
659 if (Val.isReg() && Val.getReg() != DepReg) in canPromoteToNewValueStore()
712 if (!MO.isReg()) in canPromoteToNewValueStore()
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H A DHexagonNewValueJump.cpp151 if (!Op.isReg() || !Op.isDef()) in INITIALIZE_PASS_DEPENDENCY()
176 if (II->getOperand(i).isReg() && in INITIALIZE_PASS_DEPENDENCY()
561 if (foundJump && !foundCompare && MI.getOperand(0).isReg() && in runOnMachineFunction()
568 isSecondOpReg = MI.getOperand(2).isReg(); in runOnMachineFunction()
597 if (MI.getOperand(0).isReg() && MI.getOperand(0).isDef() && in runOnMachineFunction()
648 if (!MO.isReg() || !MO.isUse()) in runOnMachineFunction()
655 if (!Op.isReg() || !Op.isUse() || !Op.isKill()) in runOnMachineFunction()
701 if (cmpInstr->getOperand(0).isReg() && in runOnMachineFunction()
704 if (cmpInstr->getOperand(1).isReg() && in runOnMachineFunction()
H A DHexagonSplitDouble.cpp179 if (MI->getOperand(1).isReg()) in isFixedInstr()
184 if (MI->getOperand(0).isReg()) in isFixedInstr()
211 if (!Op.isReg()) in isFixedInstr()
258 if (&MO == &Op || !MO.isReg() || MO.getSubReg()) in partitionRegisters()
441 if (Op.isReg() && Part.count(Op.getReg())) in isProfitable()
498 assert(Cond[1].isReg() && "Unexpected Cond vector from analyzeBranch"); in collectIndRegsForLoop()
595 if (!Op.isReg()) { in createHalfInstr()
699 assert(Op0.isReg() && Op1.isImm()); in splitImmediate()
727 assert(Op0.isReg()); in splitCombine()
735 if (!Op1.isReg()) { in splitCombine()
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H A DHexagonGenMux.cpp170 if (!MO.isReg() || MO.isImplicit()) in getDefsUses()
207 bool IsReg1 = Src1.isReg(), IsReg2 = Src2.isReg(); in getMuxOpcode()
300 Register SR1 = Src1->isReg() ? Src1->getReg() : Register(); in genMuxInBlock()
301 Register SR2 = Src2->isReg() ? Src2->getReg() : Register(); in genMuxInBlock()
359 if (!Op.isReg() || !Op.isUse()) in genMuxInBlock()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVRedundantCopyElimination.cpp80 if (CC == RISCVCC::COND_EQ && Cond[2].isReg() && in guaranteesZeroRegInBlock()
83 if (CC == RISCVCC::COND_NE && Cond[2].isReg() && in guaranteesZeroRegInBlock()
120 if (MI->isCopy() && MI->getOperand(0).isReg() && in optimizeBlock()
121 MI->getOperand(1).isReg()) { in optimizeBlock()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXProxyRegErasure.cpp97 assert(InOp.isReg() && "ProxyReg input operand should be a register."); in replaceMachineInstructionUsage()
98 assert(OutOp.isReg() && "ProxyReg output operand should be a register."); in replaceMachineInstructionUsage()
111 if (Op.isReg() && Op.getReg() == From.getReg()) { in replaceRegisterUsage()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCMCCodeEmitter.cpp49 if (MO.isReg() || MO.isImm()) in getDirectBrEncoding()
158 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getDispRIEncoding()
171 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getDispRIXEncoding()
184 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getDispRIX16Encoding()
196 assert(MI.getOperand(OpNo).isReg() && "Operand should be a register"); in getDispRIHashEncoding()
206 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getDispRIHashEncoding()
219 assert(!MO.isReg() && "Not expecting a register for this operand."); in getDispRI34PCRelEncoding()
429 if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups, STI); in encodeInstruction()
486 if (MO.isReg()) {
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/
H A DAVRMCCodeEmitter.cpp71 assert(MI.getOperand(0).isReg() && MI.getOperand(1).isReg() && in loadStorePostEncoder()
119 assert(MO.isReg()); in encodeLDSTPtrReg()
143 assert(RegOp.isReg() && "Expected register operand"); in encodeMemri()
259 if (MO.isReg()) in getMachineOpValue()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/AsmParser/
H A DM68kAsmParser.cpp155 bool isReg() const override;
311 bool M68kOperand::isReg() const { in isReg() function in M68kOperand
316 assert(isReg()); in getReg()
321 assert(isReg() && "wrong operand kind"); in addRegOperands()
547 return isReg() && checkRegisterClass(getReg(), in isAReg()
553 return isReg() && checkRegisterClass(getReg(), in isDReg()
559 return isReg() && checkRegisterClass(getReg(), in isFPDReg()
566 return isReg() && checkRegisterClass(getReg(), in isFPCReg()
579 if (Operand.isReg() && in validateTargetOperandClass()
587 if (Operand.isReg() && in validateTargetOperandClass()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/
H A DSparcInstPrinter.cpp68 if (!MI->getOperand(0).isReg()) in printSparcAliasInstr()
92 || (!MI->getOperand(0).isReg()) in printSparcAliasInstr()
118 if (MO.isReg()) { in printOperand()
156 if (Op1.isReg() && Op1.getReg() != SP::G0) { in printMemOperand()
164 PrintedFirstOperand && ((Op2.isReg() && Op2.getReg() == SP::G0) || in printMemOperand()

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