179       if (MI->getOperand(1).isReg())  in isFixedInstr()
184       if (MI->getOperand(0).isReg())  in isFixedInstr()
211     if (!Op.isReg())  in isFixedInstr()
258         if (&MO == &Op || !MO.isReg() || MO.getSubReg())  in partitionRegisters()
441           if (Op.isReg() && Part.count(Op.getReg()))  in isProfitable()
498   assert(Cond[1].isReg() && "Unexpected Cond vector from analyzeBranch");  in collectIndRegsForLoop()
595     if (!Op.isReg()) {  in createHalfInstr()
699   assert(Op0.isReg() && Op1.isImm());  in splitImmediate()
727   assert(Op0.isReg());  in splitCombine()
735   if (!Op1.isReg()) {  in splitCombine()
743   if (!Op2.isReg()) {  in splitCombine()
756   assert(Op0.isReg() && Op1.isReg());  in splitExt()
779   assert(Op0.isReg() && Op1.isReg() && Op2.isImm());  in splitShift()
904   assert(Op0.isReg() && Op1.isReg() && Op2.isReg() && Op3.isImm());  in splitAslOr()
1075     if (!Op.isReg() || !Op.isUse() || !Op.getSubReg())  in replaceSubregUses()
1100     if (!Op.isReg() || !Op.isUse())  in collapseRegPairs()