Lines Matching refs:isReg

91     assert(Target->isReg());  in SDWAOperand()
92 assert(Replaced->isReg()); in SDWAOperand()
254 assert(To.isReg() && From.isReg()); in copyRegOperand()
266 return LHS.isReg() && in isSameReg()
267 RHS.isReg() && in isSameReg()
274 if (!Reg->isReg() || !Reg->isDef()) in findSingleRegUse()
296 if (!Reg->isReg()) in findSingleRegDef()
304 if (DefMO.isReg() && DefMO.getReg() == Reg->getReg()) in findSingleRegDef()
343 if (!Reg->isReg() || !Reg->isDef()) in potentialToConvert()
390 assert(Src && (Src->isReg() || Src->isImm())); in convertToSDWA()
432 assert(Src && Src->isReg()); in convertToSDWA()
491 Operand->isReg() && in convertToSDWA()
513 if (!MO.isReg()) in convertToSDWA()
544 if (Op.isReg()) { in foldToImm()
592 if (!Src1->isReg() || Src1->getReg().isPhysical() || in matchSDWAOperand()
630 if (!Src1->isReg() || Src1->getReg().isPhysical() || in matchSDWAOperand()
692 if (!Src0->isReg() || Src0->getReg().isPhysical() || in matchSDWAOperand()
721 if (!ValSrc->isReg() || ValSrc->getReg().isPhysical() || in matchSDWAOperand()
744 if (!Op1 || !Op1->isReg() || !Op2 || !Op2->isReg()) in matchSDWAOperand()
854 assert(OrDst && OrDst->isReg()); in matchSDWAOperand()
1006 if (!Src0->isReg() && !Src0->isImm()) in isConvertibleToSDWA()
1011 if (!Src1->isReg() && !Src1->isImm()) in isConvertibleToSDWA()
1188 if (!MO.isReg()) in convertToSDWA()
1212 if (!Op.isImm() && !(Op.isReg() && !TRI->isVGPR(*MRI, Op.getReg()))) in legalizeScalarOperands()
1220 if (ST.hasSDWAScalar() && ConstantBusCount == 0 && Op.isReg() && in legalizeScalarOperands()
1231 else if (Op.isReg()) in legalizeScalarOperands()